GS8640V32T-250I GSI [GSI Technology], GS8640V32T-250I Datasheet - Page 7

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GS8640V32T-250I

Manufacturer Part Number
GS8640V32T-250I
Description
4M x 18, 2M x 32, 2M x 36 72Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
Mode Pin Functions
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.00 9/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
1st address
3rd address
4th address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
11
00
10
00
01
11
11
00
01
10
Pin Name
7/23
LBO
ZZ
FT
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
2nd address
1st address
3rd address
4th address
H or NC
L or NC
State
H
H
L
L
GS8640V18/32/36T-300/250/200/167
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
Standby, I
Interleaved Burst
Flow Through
Linear Burst
Function
Pipeline
Active
10
00
01
11
DD
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© 2004, GSI Technology
= I
SB
11
10
01
00
BPR 1999.05.18

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