GS8320V18GT-133 GSI [GSI Technology], GS8320V18GT-133 Datasheet - Page 19
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GS8320V18GT-133
Manufacturer Part Number
GS8320V18GT-133
Description
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS8320V18GT-133.pdf
(24 pages)
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, I
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Rev: 1.02 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ADSC
ADSP
CK
ZZ
Setup
Hold
SB
2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
tKC
tKC
tKH
tKH
Sleep Mode Timing Diagram
tKL
tKL
19/24
tZZS
tZZH
GS8320V18/32/36T-250/225/200/166/150/133
tZZR
SB
© 2003, GSI Technology
2. The duration of
Preliminary