GS8320Z18GT-200V GSI [GSI Technology], GS8320Z18GT-200V Datasheet - Page 9

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GS8320Z18GT-200V

Manufacturer Part Number
GS8320Z18GT-200V
Description
36Mb Pipelined and Flow Through Synchronous NBT SRAMs
Manufacturer
GSI [GSI Technology]
Datasheet
Rev: 1.02 5/2006
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Key
Current State (n)
Clock (CK)
Command
Intermediate
ƒ
Current State and Next State Definition for
Transition
Input Command Code
Intermediate State (N+1)
High Z
(Data In)
B W
Current State
n
D
R
Transition
Pipeline Mode Data I/O State Diagram
ƒ
Intermediate
Next State (n+2)
9/23
n+1
B
Intermediate
Intermediate
Intermediate
D
W
State
High Z
ƒ
R
Pipeline Mode Data I/O State Diagram
Intermediate
Notes:
1. The Hold command (CKE Low) is not
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
shown because it prevents any state change.
n+2
Next State
W
ƒ
D
Data Out
(Q Valid)
R
n+3
B
GS8320Z18/36T-xxxV
Intermediate
ƒ
© 2001, GSI Technology
Preliminary

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