GS880F32BGT-4.5 GSI [GSI Technology], GS880F32BGT-4.5 Datasheet - Page 7

• Manufacturer Part Number: GS880F32BGT-4.5
• Description: 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
• Manufacturer: GSI [GSI Technology]

Mode Pin Functions
Note:
There is a
the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.02 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
1st address
3rd address
4th address
pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
11
00
10
00
01
11
11
00
01
10
Pin Name
7/27
LBO
ZZ
FT
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
2nd address
1st address
3rd address
4th address
H or NC
L or NC
State
H
H
L
L
GS880F18/32/36BT-4.5/5/5.5/6.5/7.5
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
Standby, I
Interleaved Burst
Flow Through
Linear Burst
Function
Pipeline
Active
10
00
01
11
DD
© 2001, GSI Technology
= I
SB
11
10
01
00
BPR 1999.05.18