GS8321EV18GE-133I GSI [GSI Technology], GS8321EV18GE-133I Datasheet
GS8321EV18GE-133I
Related parts for GS8321EV18GE-133I
GS8321EV18GE-133I Summary of contents
Page 1
... Pb-Free 165-bump BGA package available Functional Description Applications The GS8321EV18/32/36E is a 37,748,736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support ...
Page 2
Bump BGA—x18 Commom I/O—Top View (Package DDQ D NC DQB V DDQ E NC DQB V DDQ F NC DQB V DDQ G ...
Page 3
Bump BGA—x32 Common I/O—Top View (Package DDQ D DQC DQC V DDQ E DQC DQC V DDQ F DQC DQC V DDQ G ...
Page 4
Bump BGA—x36 Common I/O—Top View (Package DQPC NC V DDQ D DQC DQC V DDQ E DQC DQC V DDQ F DQC DQC V DDQ G ...
Page 5
GS8321EV18/32/36E 165-Bump BGA Pin Description Symbol Type I — ...
Page 6
Register – LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown for simplicity. Rev: 1.03 ...
Page 7
Mode Pin Functions Mode Name Burst Order Control Output Register Control Power Down Control Note: There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the ...
Page 8
Byte Write Truth Table Function GW Read H Read H Write byte a H Write byte b H Write byte c H Write byte d H Write all bytes H Write all bytes L Notes: 1. All byte outputs are ...
Page 9
Synchronous Truth Table Operation Address Used Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, ...
Page 10
Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B that ADSP is tied ...
Page 11
Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles ...
Page 12
Absolute Maximum Ratings (All voltages reference Symbol Voltage in V DDQ V I/O V Voltage on Other Input Pins IN I Input Current on Any Pin IN I Output Current on Any I/O ...
Page 13
Logic Levels Parameter V Input High Voltage DD V Input Low Voltage DD V I/O Input High Voltage DDQ V I/O Input Low Voltage DDQ Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless ...
Page 14
AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
Page 15
Rev: 1.03 4/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321EV18/32/36E-250/225/200/166/150/133 15/33 © 2003, GSI Technology ...
Page 16
Operating Currents Parameter Test Conditions Mode (x32/ x36) Device Selected; All other inputs Operating ≥V or ≤ V Current IH IL Output open (x18) Standby ZZ ≥ V – 0.2 V — DD Current Device Deselected; Deselect All other inputs ...
Page 17
AC Electrical Characteristics Parameter Symbol Clock Cycle Time Clock to Output Valid Clock to Output Invalid Flow Through Clock to Output in Low-Z Setup time Hold time Clock HIGH Time Clock LOW Time Clock to Output in High ...
Page 18
Begin Read A Cont CK ADSP tS tH ADSC tS ADV tS tH Ao– Ba– tOE DQa–DQd Hi-Z Rev: 1.03 4/2005 Specifications cited are subject ...
Page 19
Begin Read A Cont tKH tKH CK ADSP tS tH ADSC tH tS ADV tS tH Ao– Ba– and E3 only sampled with ADSP and ADSC ...
Page 20
... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. ...
Page 21
JTAG Pin Descriptions Pin Pin Name I/O Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate TCK Test Clock In from the falling edge of TCK. The TMS input is sampled ...
Page 22
TDI TMS TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded ...
Page 23
Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in ...
Page 24
SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into ...
Page 25
JTAG TAP Instruction Set Summary Instruction Code EXTEST 000 Places the Boundary Scan Register between TDI and TDO. IDCODE 001 Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between ...
Page 26
JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 1.8 V Test Port Input High Voltage 1.8 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage ...
Page 27
... TCK TDI TMS TDO Parallel SRAM input JTAG Port AC Electrical Characteristics Parameter Symbol TCK Cycle Time tTKC TCK Low to TDO Valid tTKQ TCK High Pulse Width tTKH TCK Low Pulse Width tTKL TDI & TMS Set Up Time tTS TDI & TMS Hold Time ...
Page 28
Package Dimensions—165-Bump FPBGA (Package E; Variation 1) A1 TOP VIEW SEATING PLANE C ...
Page 29
Ordering Information for GSI Synchronous Burst RAMs 1 Org Part Number GS8321EV18E-250 GS8321EV18E-225 GS8321EV18E-200 GS8321EV18E-166 GS8321EV18E-150 GS8321EV18E-133 GS8321EV32E-250 1M ...
Page 30
... GS8321EV36E-166I GS8321EV36E-150I GS8321EV36E-133I GS8321EV18GE-250 GS8321EV18GE-225 GS8321EV18GE-200 GS8321EV18GE-166 GS8321EV18GE-150 GS8321EV18GE-133 GS8321EV32GE-250 GS8321EV32GE-225 GS8321EV32GE-200 GS8321EV32GE-166 GS8321EV32GE-150 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8321EV18E-166IT. ...
Page 31
... GS8321EV18GE-225I GS8321EV18GE-200I GS8321EV18GE-166I GS8321EV18GE-150I GS8321EV18GE-133I GS8321EV32GE-250I GS8321EV32GE-225I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8321EV18E-166IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...
Page 32
Org Part Number GS8321EV32E-200I GS8321EV32E-166I GS8321EV32E-150I GS8321EV32E-133I GS8321EV36E-250I GS8321EV36E-225I GS8321EV36E-200I GS8321EV36E-166I GS8321EV36E-150I ...
Page 33
... Rev: 1.03 4/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8321EV18/32/36E-250/225/200/166/150/133 36Mb Sync SRAM Datasheet Revision History Page;Revisions;Reason • Creation of new datasheet • Added parity bit designators to x18 and x36 pinouts Content • Removed address pin numbers (except 0 and 1) • ...