GS8662Q08E GSI [GSI Technology], GS8662Q08E Datasheet - Page 8
GS8662Q08E
Manufacturer Part Number
GS8662Q08E
Description
72Mb SigmaQuad-II Burst of 2 SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS8662Q08E.pdf
(35 pages)
- Current page: 8 of 35
- Download datasheet (2Mb)
SigmaQuad-II B2 SRAM DDR Write
The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of
K. A low on the Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is
clocked in with the same rising edge of K used to capture the write command. The second of the two data in transfers is captured on
the rising edge of K along with the write address. Clocking in a high on W causes a write port deselect cycle.
Rev: 1.01 9/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Address
BWx
CQ
CQ
W
R
D
C
C
Q
K
K
A
A
Write A
A+1
A+1
A
SigmaQuad-II B2 Double Data Rate SRAM Write First
B
Read B
C
D
D
8/35
Read C Write D
D+1
D+1
D
B
NOP
GS8662Q08/09/18/36E-300/250/200/167
B+1
C
E
F
F
Read E Write F
C+1
F+1
F+1
F
G
H
H
Read G Write H
© 2005, GSI Technology
H+1
H+1
Preliminary
H
E
NOP
E+1
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