HYS64V2200GU-10 SIEMENS [Siemens Semiconductor Group], HYS64V2200GU-10 Datasheet
HYS64V2200GU-10
Related parts for HYS64V2200GU-10
HYS64V2200GU-10 Summary of contents
Page 1
... PC main memory applications 1 bank and 2 bank organisation • Optimized for byte-write non-parity or ECC applications • JEDEC standard Synchronous DRAMs (SDRAM) • Fully PC board layout compatible to INTEL’ s Rev. 1.0 module specification • SDRAM Performance: • f Clock frequency (max.) CK ...
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... Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -8 speed sort SDRAM devices in TSOP44 packages to meet the PC100 requirement. Modules which use -10 parts are suitable for PC66 applications only. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’ ...
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... DQ31 119 A5 VSS 120 A7 CLK2 121 A9 NC 122 BA WP 123 NC SDA 124 VCC SCL 125 CLK1 VCC 126 NC 3 SDRAM-Modules PIN # Symbol 127 VSS 128 CKE0 129 CS3 130 DQMB6 131 DQMB7 132 NC 133 VCC 134 NC 135 NC 136 CB6 137 CB7 ...
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... CS2 DQMB2 DQM DQ0-DQ7 DQ(23:16) DQM DQMB3 DQ0-DQ7 DQ(31:24) A0-A10,BA VCC VSS RAS CAS CKE0 Note only used in the x72 ECC version Block Diagram for 2M x 64/72 SDRAM DIMM modules (HYS64/72V2200GU) Semiconductor Group HYS64(72)V2200/4220GU-8/- DQMB4 DQ(39:32 DQMB5 DQ(47:40 DQMB6 DQ(55:48) ...
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... D0 - D7,(D16) VDD 10k CKE1 D9 - D15,(D17) Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ohms except otherwise noted. Block Diagram for 4M x 64/72 SDRAM DIMM modules (HYS64/72V4220GU) Semiconductor Group HYS64(72)V2200/4220GU-8/- DQM DQMB4 ...
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... I( MHz Symbol max. 2Mx64 ICL SDRAM-Modules Limit Values min. max. 2.0 Vcc+0.3 IH – 0.5 0.8 IL 2.4 – OH – 0.4 OL – – Limit Values max. max. max. 2Mx72 4Mx64 4Mx72 ...
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... CKE>=VIH(min), tck>=tck (min.) input changed one time CKE=>VIH(min),tck=infinite, no input change Icc4 Burst length = full page, trc = infinite tck>=tck (min.), banks activated Icc5 trc>=trc(min) Icc6 CKE=<0,2V 7 SDRAM-Modules 1) 0.3V) X64 X72 Note max. 800 900 mA 1 ...
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... – 20 RCD t 70 120k – 45 RAS t 20 – – 20 RRD t 1 – CCD 8 SDRAM-Modules Unit -8-3 -10 PC100 PC66 3-2-3 2-2 – 100 – 100 MHz – 100 – 66 MHz – 6 – – 7 – – ...
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... – – 2 DQZ t 2 – 2 DPL t 5 – 5 DAL t 0 – 0 DQW 9 SDRAM-Modules Unit Note -10 PC66 2-2-2 – 10 – – 64 – – 3 – – 0 – 10) – 2 – CLK – ...
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... The specified values are valid when addresses are changed no more than once during tck(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’ s) are stable during tRC(min.). ...
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... Maximum Data Access Time from Clock at CL=1 27 Minimum Row Precharge Time 28 Minimum Row Active to Row Active delay tRRD Semiconductor Group HYS64(72)V2200/4220GU-8/-10 2 PROM - is assembled onto the module. Information about the module 2 PROM device during module production using a serial presence SPD Entry Value 128 256 SDRAM ...
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... SPD-Table (cont’ Byte# Description 29 Minimum RAS to CAS delay tRCD 30 Minimum RAS pulse width tRAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 36-61 Superset information (may be used in ...
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... Number of Row Addresses (without BS bits) 4 Number of Column Addresses (for x8 SDRAM) 5 Number of DIMM Banks 6 Module Data Width 7 Module Data Width (cont’ Module Interface Levels 9 SDRAM Cycle Time at CL=3 10 SDRAM Access time from Clock at CL=3 11 Dimm Config (Error Det/Corr.) 12 Refresh Rate/Type ...
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... SPD-Table (cont’ Byte# Description 29 Minimum RAS to CAS delay tRCD 30 Minimum RAS pulse width tRAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 36-61 Superset information (may be used in ...
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... Number of Row Addresses (without BS bits) 4 Number of Column Addresses (for x8 SDRAM) 5 Number of DIMM Banks 6 Module Data Width 7 Module Data Width (cont’ Module Interface Levels 9 SDRAM Cycle Time at CL=3 10 SDRAM Access time from Clock at CL=3 11 Dimm Config (Error Det/Corr.) 12 Refresh Rate/Type ...
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... SPD-Table (cont’ Byte# Description 29 Minimum RAS to CAS delay tRCD 30 Minimum RAS pulse width tRAS 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 36-61 Superset information (may be used in ...
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... L-DIM-168-29 SDRAM DIMM Module package 66, 6,35 2,0 Detail A 2.26 RADIUS 1.27 + 0.10 Detail D Semiconductor Group HYS64(72)V2200/4220GU-8/-10 133,35 127, 42,18 B 124 125 x) 6,35 2,0 Detail B 17 SDRAM-Modules 84 C 168 D 1,27 1,0 + 0.5 - 0,2 0, Detail ECC modules only 4,0 DM168-29.WMF ...