GS88218 GSI [GSI Technology], GS88218 Datasheet

GS88218

Manufacturer Part Number

GS88218

Description

512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs

Manufacturer

GSI [GSI Technology]

Datasheet

1.GS88218.pdf (37 pages)

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119- and 165-Bump BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip read parity checking; even or odd selectable

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119- and 165-bump BGA packages

Functional Description

Applications

The GS88218/36B is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although

of a type originally developed for Level 2 Cache applications

supporting high performance CPUs, the device now finds

application in synchronous SRAM applications, ranging from

DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,

GW) are synchronous and are controlled by a positive-edge-

triggered clock input (CK). Output enable (G) and power down

control (ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order (LBO)

input. The Burst function need not be used. New addresses can be

loaded on every cycle with no

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the

user via the FT mode . Holding the FT mode pin low places the

RAM in Flow Through mode, causing output data to bypass the

Rev: 1.02 10/2004

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through

Pipeline

3-1-1-1

2-1-1-1

degradation of chip performance.

9Mb SCD/DCD Sync Burst SRAMs

Curr (x32/x36)

Curr (x18)

tCycle

512K x 18, 256K x 36

Paramter Synopsis

1/37

-333

250

290

200

230

2.5

3.0

4.5

-300

Data Output Register. Holding FT high places the RAM in

Pipeline mode, activating the rising-edge-triggered Data Output

SCD and DCD Pipelined Reads

The GS88218/36B is a SCD (Single Cycle Deselect) and DCD

(Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one

stage less than read commands. SCD RAMs begin turning off

their outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the

SCD mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ

low) for multi-drop bus applications and normal drive strength

(ZQ floating or high) point-to-point applications. See the

Output Driver Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88218/36B operates on a 2.5 V or 3.3 V power supply.

All input are 3.3 V and 2.5 V compatible. Separate output

power (V

internal circuits and are 3.3 V and 2.5 V compatible.

230

265

185

210

2.5

3.3

5.0

-250

200

230

160

185

2.5

4.0

5.5

DDQ

GS88218/36BB/D-333/300/250/200/150

) pins are used to decouple output noise from the

-200

170

195

140

160

3.0

5.0

6.5

-150

140

160

128

145

3.8

6.7

7.5

Unit

333 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS88218

GS88218 Summary of contents

Page 1

... Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS88218/36B operates 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (V DDQ internal circuits and are 3 ...

Page 2

... DDQ N DQB SCD V DDQ LBO Bump BGA—13mm Body—1.0 mm Bump Pitch Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 ADSC ...

Page 3

... DDQ N DQD SCD V DDQ LBO Bump BGA—13mm Body—1.0 mm Bump Pitch Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 ADSC ...

Page 4

... GS88236B Pad Out—119-Bump BGA—Top View (Package Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 ADSP DDQ ADSC ...

Page 5

... GS88218B Pad Out—119-Bump BGA—Top View (Package Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 ADSP DDQ ADSC ...

Page 6

... GS88218/36 BGA Pin Description Symbol Type I — NC — ADV I ADSC, ADSP LBO FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low ...

Page 7

... Power Down ZZ Control Note: Only x36 version shown for simplicity. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 GS88218/36B ( Block Diagram Counter Load Register D Q Register ...

Page 8

... GS88218/36B ( x32 Mode Block Diagram Register A0– LBO ADV CK ADSC ADSP Power Down ZZ Control Note: Only x36 version shown for simplicity. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 9

... ZZ H Interleaved Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 9/37 GS88218/36BB/D-333/300/250/200/150 Function Linear Burst Interleaved Burst Active Standby A[1:0] A[1:0] A[1:0] A[1: ...

Page 10

... may be used in any combination with BW to write single or multiple bytes. D 10/37 GS88218/36BB/D-333/300/250/200/150 B B Notes ...

Page 11

... Key None X H External R L External R L External W L Next CR X Next CR H Next CW X Next CW H Current X Current H Current X Current H 11/37 GS88218/36BB/D-333/300/250/200/150 3 ADSP ADSC ADV ...

Page 12

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write CR CW 12/37 GS88218/36BB/D-333/300/250/200/150 First Read Burst Read BW, and GW) control inputs, and ...

Page 13

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 13/37 GS88218/36BB/D-333/300/250/200/150 First Read Burst Read CR © 2002, GSI Technology ...

Page 14

... Storage Temperature Symbol Min. V 3.0 DD3 V 2.3 DD2 V 3.0 DDQ3 V 2.3 DDQ2 +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 14/37 GS88218/36BB/D-333/300/250/200/150 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3 ...

Page 15

... The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica- tions quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < V Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 Symbol Min. Typ. V 2.0 — ...

Page 16

... Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 16/37 GS88218/36BB/D-333/300/250/200/150 50% tKC Typ. Max. Unit 30pF © 2002, GSI Technology ...

Page 17

... ZZ Input Current FT, SCD, ZQ Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 Symbol Test Conditions ≥ V ...

Page 18

... SB Through I Pipeline 95 100 90 DD Flow Through , and V operation. DD3 DD2 DDQ3 DDQ2 18/37 GS88218/36BB/D-333/300/250/200/150 -300 -250 -200 –40 –40 – 85°C 70°C 85°C 70°C 85°C 70°C 250 200 220 170 190 140 ...

Page 19

... asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 -333 -300 Symbol ...

Page 20

... ADSC initiated read and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 20/37 GS88218/36BB/D-333/300/250/200/150 Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) © 2002, GSI Technology Deselect tKQX tHZ Q(C+3) ...

Page 21

... Flow Through Mode Timing (SCD) Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 21/37 GS88218/36BB/D-333/300/250/200/150 Cont Deselected with E1 Q(C+1) Q(C+2) Q(C+3) Q(C) © 2002, GSI Technology Deselect tHZ tKQX ...

Page 22

... Pipeline Mode Timing (DCD) Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKL tKL tKH tKH tKC tKC ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH tLZ Q(A) D(B) 22/37 GS88218/36BB/D-333/300/250/200/150 Deselect Deselect Deselected with E1 tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2002, GSI Technology tKQX ...

Page 23

... Flow Through Mode Timing (DCD) Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read masks ADSP E1 masks ADSP tH tS tOHZ tLZ Q(A) D(B) Q(C) 23/37 GS88218/36BB/D-333/300/250/200/150 Deselect tH Deselected with E1 tKQX tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2002, GSI Technology ...

Page 24

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 24/37 GS88218/36BB/D-333/300/250/200/150 2. The duration of SB tZZR . The JTAG output DD . TDO should be left unconnected. SS © 2002, GSI Technology ...

Page 25

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 Description 25/37 © 2002, GSI Technology ...

Page 26

... Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 JTAG TAP Block Diagram · ...

Page 27

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Not Used Configuration 27/37 GS88218/36BB/D-333/300/250/200/150 GSI Technology I/O JEDEC Vendor ID Code © 2002, GSI Technology ...

Page 28

... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 28/37 GS88218/36BB/D-333/300/250/200/150 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2002, GSI Technology ...

Page 29

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 29/37 © 2002, GSI Technology ...

Page 30

... Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 Conditions V – V/ns ...

Page 31

... OLJC + V not to exceed .6 V maximum, with a pulse width not to exceed 20% tTKC. DDn supply. DDQ JTAG Port Timing Diagram tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS 31/37 GS88218/36BB/D-333/300/250/200/150 Min. Max. Unit Notes V +0.3 2.0 DD3 0.8 –0.3 0 +0.3 DD DD2 0 –0.3 DD –300 ...

Page 32

... For information regarding the Boundary Scan Chain obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com. Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 Min Max Unit 50 — ...

Page 33

... SEATING PLANE C Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 BOTTOM VIEW A1 Ø0. Ø0. Ø0.60~0.90 (119x 7.62 14±0.10 A 0.20(4x) ...

Page 34

... SEATING PLANE C Rev: 1.02 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS88218/36BB/D-333/300/250/200/150 BOTTOM VIEW Ø0. Ø0. Ø0.40~0.50 (165x 1.0 10.0 13±0.07 B 0.20(4x) ...

Page 35

... GS88236BB-250I 256K x 36 GS88236BB-200I 256K x 36 GS88236BB-150I 512K x 18 GS88218BD-333 512K x 18 GS88218BD-300 512K x 18 GS88218BD-250 512K x 18 GS88218BD-200 512K x 18 GS88218BD-150 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88236B-150IT. ...

Page 36

... GS88236BD-200 256K x 36 GS88236BD-150 512K x 18 GS88218BD-333I 512K x 18 GS88218BD-300I 512K x 18 GS88218BD-250I 512K x 18 GS88218BD-200I 512K x 18 GS88218BD-150I 256K x 36 GS88236BD-333I 256K x 36 GS88236BD-300I 256K x 36 GS88236BD-250I 256K x 36 GS88236BD-200I 256K x 36 GS88236BD-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS88236B-150IT. ...

Page 37

... Removed erroneous speed bins • Added 333/300 MHz speed bins Content/Format • Basic format updates • Removed Preliminary banner due to qualification of parts • \Corrected copywrite date • Updated mechanical drawings and added variation numbers Content to ordering information 37/37 GS88218/36BB/D-333/300/250/200/150 Page;Revisions;Reason © 2002, GSI Technology ...

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