GS882Z18B-100 ETC [List of Unclassifed Manufacturers], GS882Z18B-100 Datasheet
GS882Z18B-100
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GS882Z18B-100 Summary of contents
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... NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc. Functional Description The GS882Z818/36B is an 8Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles ...
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GS882Z36 Pad Out Rev: 1.15 6/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 119-Bump BGA—Top View 1 ...
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GS882Z18 Pad Out Rev: 1.15 6/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com 119-Bump BGA—Top View 1 ...
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GS882Z18/36 BGA Pin Description Pin Location Symbol P4, N4 A2, A3, A5, A6, B3, B5, C2, C3, C5, C6, G4, R2, R6, T3 T2, T6 T2, T6 K7, L7, N7, P7, K6, L6, M6, N6 H7, ...
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GS882Z18/36 BGA Pin Description Pin Location Symbol J2, C4, J4, R4, J6 D3, E3, F3, H3, K3, M3, N3, P3, D5, E5, F5, H5, K5, M5, N5, P5 A1, F1, J1, M1, U1, A7, F7, J7, ...
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... A B Cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock ...
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... Dummy read and write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active Write operation is performed can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during Write cycles. 4. ...
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Pipeline and Flow Through Read-Write Control State Diagram New Read R R Burst Read B Key Input Command Code ƒ Transition Current State (n) Next State (n+1) n Clock (CK) Command Current State Current State and Next State Definition for ...
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Pipeline Mode Data I/O State Diagram Intermediate B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Intermediate State (N+1) Clock (CK) Command Current State and Next State Definition for Rev: 1.15 6/2001 Specifications cited ...
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Flow Through Mode Data I/O State Diagram B W High Z (Data In) Key Input Command Code ƒ Transition Current State (n) Clock (CK) Command Current State and Next State Definition for: Rev: 1.15 6/2001 Specifications cited are subject to ...
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... SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode ...
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... During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time. ...
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... Initialization of the memory should be implemented to avoid this issue. In x18/x36 mode this SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are reported one clock cycle later ...
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Mode ( Write Parity Error Output Timing Diagram Rev: 1.15 6/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com ...
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Absolute Maximum Ratings (All voltages reference Symbol Description V Voltage Voltage in V DDQ DDQ V Voltage on Clock Input Pin CK V Voltage on I/O Pins I/O V Voltage on ...
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... Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP) Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper- ature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1 Rev: 1 ...
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AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Output load Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. ...
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Operating Currents Parameter Test Conditions Device Selected; Operating All other inputs Current Output open Standby ZZ V – 0 Current Device Deselected; Deselect All other inputs Current Rev: ...
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AC Electrical Characteristics Parameter Clock Cycle Time Clock to Output Valid Pipeline Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Clock to Output Valid Flow- through Clock to Output Invalid Clock to Output in Low-Z Clock ...
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Pipeline Mode Read/Write Cycle Timing CKE ADV – – Write Write COMMAND D(A2) D(A1) ...
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Pipeline Mode No-Op, Stall and Deselect Timing CKE ADV – Write D(A1) COMMAND *Note High (False ...
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Flow Through Mode Read/Write Cycle Timing CKE ADV – D(A1 Write COMMAND D(A1) *Note High ...
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Flow Through Mode No-Op, Stall and Deselect Timing CKE ADV W Bn – Write COMMAND D(A1) *Note High (False ...
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JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG), but does not implement all of the functions required for ...
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Boundary Scan Register Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found ...
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Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions, are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in ...
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SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the Instruc- tion Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the ...
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JTAG TAP Instruction Set Summary Instruction Code Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. EXTEST 000 This RAM does not implement 1149.1 EXTEST function. *Not 1149.1 Compliant * IDCODE 001 Preloads ID Register and places it between ...
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JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Notes: 1. Include scope and jig capacitance. JTAG Port Timing Diagram tTKH tTKL TCK TMS TDI TDO tTKQ JTAG ...
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GS882Z18/36B BGA Boundary Scan Register Bump x36 x18 x36 x18 n ...
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FLXDrive Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 0.0 -20.0 -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0 Rev: 1.15 6/2001 Specifications cited are subject to ...
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Package Dimensions—119-Bump PBGA A Pin 1 Corner P N Top View Side View Rev: 1.15 6/2001 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Bottom View Package Dimensions—119-Bump PBGA Symbol ...
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... GS882Z18B-80 512K x 18 GS882Z18B-66 256K x 36 GS882Z36B-11 256K x 36 GS882Z36B-100 256K x 36 GS882Z36B-80 256K x 36 GS882Z36B-66 512K x 18 GS882Z18B-11I 512K x 18 GS882Z18B-100I 512K x 18 GS882Z18B-80I 512K x 18 GS882Z18B-66I 256K x 36 GS882Z36B-11I 256K x 36 GS882Z36B-100I 256K x 36 GS882Z36B-80I 256K x 36 GS882Z36B-66I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “ ...
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Revision History Types of Changes DS/DateRev. Code: Old; Format or Content New GS882Z818/36BRev1.04h 5/ 1999; 1.05 9/1999 GS882Z818/36B 1.05 9/ 1999K/ 1.06 10/1999 GS882Z818/36B 1.06 9/ 1999K 1.07 1/2000L Rev.1.10; 882Z18_r1_11 Content/Format 882Z18_r1_11; 882Z18_r1_12 882Z18_r1_12; 882Z18_r1_13 882Z18_r1_13; 882Z18_r1_14 882Z18_r1_14; 882Z18_r1_15 ...