ACE24C16ADPTH ACE [ACE Technology Co., LTD.], ACE24C16ADPTH Datasheet - Page 9
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ACE24C16ADPTH
Manufacturer Part Number
ACE24C16ADPTH
Description
Two-wire Serial EEPROM
Manufacturer
ACE [ACE Technology Co., LTD.]
Datasheet
1.ACE24C16ADPTH.pdf
(15 pages)
Read Operations
select bit in the device address word is set to one. There are three read operations: current address
read, random address read and sequential read.
Current Address Read
write operation, incremented by one. This address stays valid between operations as long as the chip
power is maintained. The address “roll over” during read is from the last byte of the last memory page
to the first byte of the first page. The address “roll over” during write is from the last byte of the current
page to the first byte of the same page.
the EEPROM, the current address data word is serially clocked out. The microcontroller does not
respond with an input zero but does generate a following stop condition (refer to Figure 10).
Random Read
device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current
address read by sending a device address with the read/write select bit high. The EEPROM
acknowledges the device address and serially clocks out the data word. The microcontroller does not
respond with a zero but does generate a following stop condition (refer to Figure 11).
Sequential Read
microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM
receives an acknowledge, it will continue to increment the data word address and serially clock out
sequential data words. When the memory address limit is reached, the data word address will “roll
over” and the sequential read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condition (refer to
Figure 12).
Read operations are initiated the same way as write operations with the exception that the read/write
The internal data word address counter maintains the last address accessed during the last read or
Once the device address with the read/write select bit set to one is clocked in and acknowledged by
A random read requires a “dummy” byte write sequence to load in the data word address. Once the
Sequential reads are initiated by either a current address read or a random address read. After the
16K
MSB
1
0
Figure 7.Device Address
1
Technology
0
P
2
P
1
P
0
R/W
LSB
Two-wire Serial EEPROM
ACE24C16A
VER 1.2
9