PPC440SP-AFC533C AMCC [Applied Micro Circuits Corporation], PPC440SP-AFC533C Datasheet
PPC440SP-AFC533C
Related parts for PPC440SP-AFC533C
PPC440SP-AFC533C Summary of contents
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... On-chip 256-KB SRAM configurable as L2 Cache or Ethernet Packet/Code store memory • Selectable Processor:Bus clock ratios (Refer to the Clocking chapter in the PPC440SP Embedded Processor User’s Manual for details) • Supports Chip Selects) of 64-bit/32- bit SDRAM with ECC – ...
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... PowerPC 440SP Embedded Processor Contents Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PPC440SP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 On-Chip SRAM/L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DDR PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DDR1/DDR2 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 External Peripheral Bus Controller (EBC Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2O/DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Optional RAID 5 and RAID 6 Acceleration Hardware ...
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... Revision 1.23 - Sept 26, 2006 Data Sheet Figures Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. PPC440SP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. 29mm, 783-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 5. Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 6. Output Delay and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 7. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 8 ...
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... The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. See the PPC440SP Embedded Processor User’s Manual for details about accessing these registers. Note: Raid-enabled versions (Product Feature = R) require a RAID key license. ...
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... OPB interfaces up to 83.33MHz, 333MB/s Address Maps The PPC440SP incorporates two address maps. The first is a fixed processor system memory address map. This address map defines the possible contents of various processor accessible address regions. The second address map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the PPC440SP processor through the use of mtdcr and mfdcr instructions ...
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PowerPC 440SP Embedded Processor Table 1. System Memory Address Map (Sheet Function DDR SDRAM 1 SRAM Local Memory (LL) Reserved I2O Registers DMA 0 Registers DMA 1 Registers Internal PLB Interfaces (LL) I20/DMA Buffers Reserved XOR/DMA2 Reserved ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 1. System Memory Address Map (Sheet Function Reserved PCIX0 I/O PCIX1 I/O PCIX2 I/O PCIX0 Addressing Config. Regs PCIX1 Addressing Config. Regs PCIX2 Addressing Config. Regs PCIX0 Core ...
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PowerPC 440SP Embedded Processor Table 2. DCR Address Map (4KB of Device Configuration Registers) Function 1 Total DCR Address Space By function: Reserved Clocking Power On Reset System DCRs Memory Controller External Bus Controller Reserved SRAM L2 Controller Memory Queue ...
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Revision 1.23 - Sept 26, 2006 Data Sheet PowerPC 440 Processor Core The PowerPC 440 processor core is designed for high-end applications such as RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, and so on the first ...
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PowerPC 440SP Embedded Processor – 32- and 64-byte burst transfers – 166MHz, maximum 5.2GB/s (simultaneous read and write) – Processor:Bus clock ratios of N:1 and N:2 • OPB – Dynamic bus sizing: 32-, 16-, and 8-bit data path – 32-bit ...
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Revision 1.23 - Sept 26, 2006 Data Sheet • PCI Power Management Version 1.1 • PCI arbitration function with PCI-X Mode 2 support (optional) • PCI register set addressable both from on-chip processor and PCI device sides • Ability to ...
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PowerPC 440SP Embedded Processor • 24-bit address, 16MB address space • Peripheral Device pacing with external “Ready” • Latch data on Ready, synchronous or asynchronous • Programmable access timing per device – 256 Wait States for non-burst – 32 Burst ...
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... The two-way crossbar bus architecture can perform data read and write operations simultaneously, resulting in extremely high throughput. RAID 6 capability is available only with the RAID-enabled part numbers (PPC440SP-RpCfffC) as indicated in the ordering information section of this data sheet. For more information about the RAID 6 implementation, description, and configuration of the acceleration hardware, refer to the following AMCC documents: • ...
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PowerPC 440SP Embedded Processor Features include: • Two IIC interfaces provided ‚ • Support for Philips Semiconductors I • Operation at 100kHz or 400kHz • 8-bit data • 10- or 7-bit address • Slave transmitter and receiver • Master transmitter ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Universal Interrupt Controller (UIC) Two cascaded Universal Interrupt Controllers (UIC) process internal on-chip and external processor interrupts. Note: Processor specific interrupts (for example, page faults) do not use UIC resources. Features include: ...
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... ® PPC440SP Part Number xpCfffC AAAAAAAA 29.0 ± 0 0.6 ± 0.1 SOLDERBALL x 783 Revision 1.23 - Sept 26, 2006 Data Sheet 1.00 TYP 0.4 MIN 3.27 MAX AMCC Proprietary ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Signal Lists This section contains two tables that list external signals. Table 3 lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 2 of 30) Signal Name DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 3 of 30) Signal Name ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 AMCC Proprietary PowerPC 440SP Embedded Processor Ball Interface Group AC24 Y23 Y21 AC23 ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 4 of 30) Signal Name EMCCD EMCCrS EMCMDClk EMCMDIO EMCRefClk EMCRxClk EMCRxD0 EMCRxD1 EMCRxD2 EMCRxD3 EMCRxD4 EMCRxD5 EMCRxD6 EMCRxD7 EMCRxDV EMCRxErr EMCTxClk EMCGTxClk EMCTxD0 EMCTxD1 EMCTxD2 EMCTxD3 EMCTxD4 EMCTxD5 EMCTxD6 ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 5 of 30) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 6 of 30) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 7 of 30) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 8 of 30) Signal Name [GPIO00] [TrcClk] PCIX0Req2 [GPIO01] [TrcBS0] PCIX0Req3 [GPIO02] [TrcBS1] PCIX0Gnt2 [GPIO03] [TrcBS2] PCIX0Gnt3 [GPIO04] [TrcES0] PCIX1Req2 [GPIO05] [TrcES1] PCIX1Req3 [GPIO06] [TrcES2] PCIX1Gnt2 [GPIO07] [TrcES3] PCIX1Gnt3 [GPIO08] ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 9 of 30) Signal Name IIC0SClk IIC0SDA IIC1SClk IIC1SDA IRQ0 [GPIO11] [TrcTS2] IRQ1 [GPIO12] [TrcTS3] IRQ2 [GPIO13] [TrcTS4] IRQ3 [GPIO14] [TrcTS5] IRQ4 [GPIO15] [TrcTS6] IRQ5 [GPIO16] ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 10 of 30) Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 11 of 30) Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 12 of 30) Signal Name MemODT0 MemODT1 MemVRef0 MemVRef1 No ball ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 13 of 30) Signal Name P0V DD P0V DD P0V DD P0V DD P0V DD P0V DD P0V DD P0V DD P0V DD P0V DD P0V ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 14 of 30) Signal Name PCIX0Ack64 [PCIX0ECC1] PCIX0AD00 PCIX0AD01 PCIX0AD02 PCIX0AD03 PCIX0AD04 PCIX0AD05 PCIX0AD06 PCIX0AD07 PCIX0AD08 PCIX0AD09 PCIX0AD10 PCIX0AD11 PCIX0AD12 PCIX0AD13 PCIX0AD14 PCIX0AD15 PCIX0AD16 PCIX0AD17 PCIX0AD18 PCIX0AD19 PCIX0AD20 PCIX0AD21 PCIX0AD22 ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 15 of 30) Signal Name PCIX0AD32 PCIX0AD33 PCIX0AD34 PCIX0AD35 PCIX0AD36 PCIX0AD37 PCIX0AD38 PCIX0AD39 PCIX0AD40 PCIX0AD41 PCIX0AD42 PCIX0AD43 PCIX0AD44 PCIX0AD45 PCIX0AD46 PCIX0AD47 PCIX0AD48 PCIX0AD49 PCIX0AD50 PCIX0AD51 PCIX0AD52 ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 16 of 30) Signal Name PCIX0BE0 PCIX0BE1 PCIX0BE2 PCIX0BE3 PCIX0BE4 PCIX0BE5 PCIX0BE6 PCIX0BE7 PCIX0CalG0 PCIX0CalG1 PCIX0CalR0 PCIX0CalR1 PCIX0Cap PCIX0Clk PCIX0DevSel [PCIX0ECC0] PCIX0Par [PCIX0ECC1] PCIX0Ack64 PCIX0ECC2 PCIX0ECC3 PCIX0ECC4 PCIX0ECC5 [PCIX0ECC6] PCIX0Req64 ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 17 of 30) Signal Name PCIX0M66En PCIX0Par [PCIX0ECC0] PCIX0Par64 [PCIX0ECC7] PCIX0PErr PCIX0Req0 [GPIO20] PCIX0Req1 [GPIO21] PCIX0Req2 [GPIO00] [TrcClk] PCIX0Req3 [GPIO01] [TrcBS0] PCIX0Req64 [PCIX0ECC6] PCIX0Reset PCIX0SErr PCIX0Stop ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 18 of 30) Signal Name PCIX1Ack64 [PCIX1ECC1] PCIX1AD00 PCIX1AD01 PCIX1AD02 PCIX1AD03 PCIX1AD04 PCIX1AD05 PCIX1AD06 PCIX1AD07 PCIX1AD08 PCIX1AD09 PCIX1AD10 PCIX1AD11 PCIX1AD12 PCIX1AD13 PCIX1AD14 PCIX1AD15 PCIX1AD16 PCIX1AD17 PCIX1AD18 PCIX1AD19 PCIX1AD20 PCIX1AD21 PCIX1AD22 ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 19 of 30) Signal Name PCIX1AD32 PCIX1AD33 PCIX1AD34 PCIX1AD35 PCIX1AD36 PCIX1AD37 PCIX1AD38 PCIX1AD39 PCIX1AD40 PCIX1AD41 PCIX1AD42 PCIX1AD43 PCIX1AD44 PCIX1AD45 PCIX1AD46 PCIX1AD47 PCIX1AD48 PCIX1AD49 PCIX1AD50 PCIX1AD51 PCIX1AD52 ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 20 of 30) Signal Name PCIX1BE0 PCIX1BE1 PCIX1BE2 PCIX1BE3 PCIX1BE4 PCIX1BE5 PCIX1BE6 PCIX1BE7 PCIX1CalG0 PCIX1CalG1 PCIX1CalR0 PCIX1CalR1 PCIX1Cap PCIX1Clk PCIX1DevSel [PCIX1ECC0] PCIX1Par [PCIX1ECC1] PCIX1Ack64 PCIX1ECC2 PCIX1ECC3 PCIX1ECC4 PCIX1ECC5 [PCIX1ECC6] PCIX1Req64 ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 21 of 30) Signal Name PCIX1Par [PCIX1ECC0] PCIX1Par64 [PCIX1ECC7] PCIX1PErr PCIX1Req0 [GPIO24] PCIX1Req1 [GPIO25] PCIX1Req2 [GPIO04] [TrcES0] PCIX1Req3 [GPIO05] [TrcES1] PCIX1Req64 [PCIX1ECC6] PCIX1Reset PCIX1SErr PCIX1Stop PCIX1TRDY ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 22 of 30) Signal Name PCIX2AD00 PCIX2AD01 PCIX2AD02 PCIX2AD03 PCIX2AD04 PCIX2AD05 PCIX2AD06 PCIX2AD07 PCIX2AD08 PCIX2AD09 PCIX2AD10 PCIX2AD11 PCIX2AD12 PCIX2AD13 PCIX2AD14 PCIX2AD15 PCIX2AD16 PCIX2AD17 PCIX2AD18 PCIX2AD19 PCIX2AD20 PCIX2AD21 PCIX2AD22 PCIX2AD23 PCIX2AD24 ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 23 of 30) Signal Name PCIX2BE2 PCIX2BE3 PCIX2CalG0 PCIX2CalR0 PCIX2Cap PCIX2Clk PCIX2DevSel [PCIX2ECC0] PCIX2Par PCIX2ECC1 PCIX2ECC2 PCIX2ECC3 PCIX2ECC4 PCIX2ECC5 PCIX2ECC6 PCIX2Frame PCIX2Gnt0 [GPIO26] PCIX2Gnt1 [GPIO27] PCIX2IDSel ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 24 of 30) Signal Name PerAddr00 PerAddr01 PerAddr02 PerAddr03 PerAddr04 PerAddr05 PerAddr06 PerAddr07 PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerBE0 ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 25 of 30) Signal Name PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerErr PerOE PerPar0 PerReady [GPIO08] [TrcES4] PerR/W PerWE PSRO PSRO PSRO PSRO RAS ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 26 of 30) Signal Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 27 of 30) Signal Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 28 of 30) Signal Name TCK TDI TDO TestEn TmrClk TMS [TrcClk] [GPIO00] PCIX0Req2 [TrcBS0] [GPIO01] PCIX0Req3 [TrcBS1] [GPIO02] PCIX0Gnt2 [TrcBS2] [GPIO03] PCIX0Gnt3 [TrcES0] [GPIO04] PCIX1Req2 [TrcES1] [GPIO05] PCIX1Req3 [TrcES2] ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 3. Signals Listed Alphabetically (Sheet 29 of 30) Signal Name UART1_DSR/CTS UART1_RTS/DTR UART1_Rx [GPIO30] UART1_Tx [GPIO31] [UART2_Rx] [GPIO16] IRQ5 [UART2_Tx] [GPIO17] PerBE0 UARTSerClk ...
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PowerPC 440SP Embedded Processor Table 3. Signals Listed Alphabetically (Sheet 30 of 30) Signal Name ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Signal List—Ball Assignment Order In the following table, only the primary (default) signal name is shown for each pin. Multiplexed pins are marked with an asterisk (*). To determine the other signals ...
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PowerPC 440SP Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball E01 EMCTxClk F01 E02 GND F02 E03 EMCCrS F03 E04 EMCMDIO F04 V E05 F05 DD E06 PerData5 F06 E07 GND ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 4. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball J01 EMCRxErr K01 J02 GND K02 J03 SysClk K03 J04 PerAddr00 K04 V J05 K05 DD J06 ...
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PowerPC 440SP Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball N01 PCIX2ECC4 P01 N02 PCIX2TRDY P02 N03 GND P03 * N04 P04 PCIX2Req1 V N05 P05 DD N06 PerAddr11 P06 N07 ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 4. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball V U01 V01 DD U02 PCIX2BE3 V02 U03 PCIX2AD25 V03 U04 PCIX2AD28 V04 * U05 V05 PCIX2Req0 ...
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PowerPC 440SP Embedded Processor Table 4. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball AA01 PCIX2AD09 AB01 AA02 PCIX2BE1 AB02 AA03 PCIX2AD12 AB03 AA04 PCIX2AD13 AB04 AA05 PCIX2AD23 AB05 AA06 PCIX2ECC5 AB06 AA07 PCIX2ECC2 AB07 ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 4. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball AE01 PCIX0AD30 AF01 AE02 PCIX0AD31 AF02 AE03 PCIX0AD27 AF03 AE04 PCIX2ECC6 AF04 AE05 PCIX0AD29 AF05 AE06 PCIX0BE3 ...
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... PowerPC 440SP Embedded Processor Signal Description The PPC440SP embedded controller is packaged in a 783-ball flip-chip plastic ball grid array (FC-PBGA). The following table describes the package level pinout. Table 5. Pin Summary Signal pins, non-multiplexed Signal pins, multiplexed PxV SV In the table “Signal Functional Description” on page 56, each I/O signal is listed along with a short description of its function. Active-low signals (for example, RAS) are marked with an overline. Please see “ ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Multiplexed Signals Some signals are multiplexed on the same pin so that the pin can be used for different functions. The signal names shown in Signal Functional Description are not accompanied by ...
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PowerPC 440SP Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is ...
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PowerPC 440SP Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not ...
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... PerData0 is the most significant bit (msb). Used by peripheral controller or DMA controller depending upon the type of transfer involved. When the PerOE PPC440SP is the bus master, it enables the selected device to drive the bus. PerPar0 External peripheral data bus byte parity. Used by a peripheral slave to indicate it is ready to PerReady transfer data ...
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PowerPC 440SP Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not ...
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... SysReset system reset. A system reset can also be initiated by software. HISRRst Hardware initiated self-refresh and system reset. External Reset. During the PPC440SP’s reset phase, ExtReset this signal is at down level. TestEn Test Enable. TmrClk Processor timer external input clock ...
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PowerPC 440SP Embedded Processor Table 6. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not ...
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... Storage temperature range Case temperature under bias Notes: 1. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440SP. A separate filter, as shown below, is recommended for each voltage This value is not a specification of the operational temperature range stress rating only. ...
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... PowerPC 440SP Embedded Processor Table 8. Package Thermal Specifications Thermal resistance values for the PPC440SP package in a convection environment are as follows: Parameter Junction-to-case thermal resistance Case-to-ambient thermal resistance (w/o heat sink) Junction-to-ball (typical) Notes: 1. Case temperature measured at top center of case surface with device soldered to circuit board. For this part the junction C temperature and the case temperature are essentially identical ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 9. Recommended DC Operating Conditions (Sheet Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter Input Logic ...
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... The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440SP. See “Absolute Maximum Ratings” on page 63. 4. Power supply sequencing recommended that the 1.5V Vdd of the core reach its nominal value before applying power to the I/Os ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 11. DC Power Supply Loads Parameter V (1.5V) active operating current DD OV (3.3V) active operating current DD PxV (3.3V) active operating current DD PxV (1.5V) active operating current DD SV ...
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PowerPC 440SP Embedded Processor Table 12. Clocking Specifications Symbol Parameter SysClk Input F Frequency C T Period C T Edge stability (cycle-to-cycle jitter High time CH T Low time CL ≥ Note: Input slew rate 1V/ns PLL VCO ...
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... Ethernet operation is unaffected. 3. IIC operation is unaffected. Important the system designer to ensure that any SSCG used with the PPC440SP meets the above requirements and does not adversely affect other aspects of the system. AMCC Proprietary ...
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... OPB clock. The internal OPB clock runs at an integral divisor ratio of the frequency of OPB the PLB clock. The maximum OPB clock frequency is 83.33 MHz. Refer to the Clocking chapter of the PPC440SP Embedded Processor User’s Manual for details. 2. When the PCI-X interface is used to support a legacy PCI interface, the maximum PCIXClk frequency is 66.66MHz. ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Input/Output Timing These timing diagrams illustrate the relationship of the timing parameters defined in the I/O Specification tables that follow. Figure 5. Input Setup and Hold Timing Waveform Clock Inputs Figure 6. ...
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PowerPC 440SP Embedded Processor Table 14. I/O Specifications—All Speeds (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 14. I/O Specifications—All Speeds (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133.33MHz. ...
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PowerPC 440SP Embedded Processor Table 14. I/O Specifications—All Speeds (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 15. I/O Specifications—533MHz Notes: 1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns. Input (ns) Signal Setup Time Hold Time (T ...
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... In a typical system, users advance MemClkOut by 90×. This depends on the specific application and requires a thorough understanding of the memory system in general (refer to the DDR SDRAM controller chapter in the PPC440SP Embedded Processor User’s Manual). In the following sections, the label MemClkOut0(0) refers to MemClkOut0 when it has not been phase-shifted, and MemClkOut0(90) refers to MemClkOut0 when it has been phase-advanced 90° ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 16. DDR SDRAM Output Driver Specifications Signal Path Write Data MemData00:07 MemData08:15 MemData16:23 MemData24:31 MemData32:39 MemData40:47 MemData48:55 MemData56:63 ECC0:7 DM0:8 MemClkOut0 MemAddr00:12 BA0:1 RAS CAS WE BankSel0:3 ClkEn0:3 DQS0:8 AMCC Proprietary ...
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PowerPC 440SP Embedded Processor DDR SDRAM Write Operation The following timing chart shows the relationship between the signals involved in a DDR write operation. Figure 8. DDR SDRAM Write Cycle Timing PLB Clk MemClkOut Addr/Cmd DQS MemData T = Setup ...
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Revision 1.23 - Sept 26, 2006 Data Sheet DDR SDRAM Clock to Write DQS Timing—T Note 1: All of the DQS signals are referenced to MemClkOut. Note 2: Clock speed is 333 MHz. Note 3: The TDS values in the ...
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... The read of the incoming data from the SDRAM is done on the rising and falling edges of the differential DQS signal. The data must be centered on these edges for correct operation. The PPC440SP can delay in very small increments the DQS by means of the programming of the MCIF0_RODC[RQFD] register field. ...
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Revision 1.23 - Sept 26, 2006 Data Sheet Table 20. DDR SDRAM I/O Read Timing—T Notes and T are measured under worst case conditions Clock speed for the values in the table is 333.33MHz. 3. ...
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PowerPC 440SP Embedded Processor The following figure shows the timing relationship between SDRAM DDR Data at the input pin and the store of the data in stage 1. Figure 11. DDR SDRAM Read Cycle Timing Example DDR 1X Clock DDR ...
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... During reset, if the serial device is enabled, initial conditions can be read from a ROM connected to the IIC0 port. In this case, at the de-assertion of SysReset, the PPC440SP sequentially reads bytes from the ROM device on the IIC0 port and sets the SDR0_SDSTP0 - SDR0_SDSTP7 registers accordingly. ...
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PowerPC 440SP Embedded Processor Document Revision History Revision Date Corrected Package Thermal Specifications table where the letter q appeared instead of the symbol 1.23 Sept 26, 2006 for theta. 1.22 Sept 22, 2006 Updated Recommended DC Operating Conditions table. 1.21 ...
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... Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC’ ...