RHF1401_12 STMICROELECTRONICS [STMicroelectronics], RHF1401_12 Datasheet - Page 34

• Manufacturer Part Number: RHF1401_12
• Description: Rad-hard 14-bit 30 Msps A/D converter
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

User manual
3.5
3.5.1
3.5.2
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Operating modes
Extra functionalities are provided to simplify the application board as much as possible. The
operating modes offered by the RHF1401 are described in
Table 14.
1. High impedance.
Digital inputs
Data format select bit (DFSB): when set to low level (V
a two’s complement digital output MSB. This can be of interest when performing some
further signal processing. When set to high level (V
output coding (see
Output enable bit (OEB): when set to low level (V
set to high level (V
converter goes on sampling. When OEB is set to a low level again, the data arrives on the
output with a very short T
Figure 11: Timing diagram
Reference mode control (REFMODE): this allows the internal or external settings of the
voltage references VREFP and INCM. REFMODE = 0 for internal references,
REFMODE = 1 for external references (and disables both references VREFP and INCM).
Digital outputs
Out of range (OR): this function is implemented on the output stage in order to set an "out-
of-range" flag whenever the digital data is over the full-scale range. Typically, there is a
detection of all data at ‘0’ or all data at ‘1’. It sets an output signal OR, which is in a low level
state (V
data read by the ADC is out of range.
Data ready (DR): the Data Ready output is an image of the clock being synchronized on the
output data (D0 to D13). This is a very helpful signal that simplifies the synchronization of
the measurement equipment of the controlling DSP. Like all other digital outputs, DR goes
into high impedance when OEB is set to a high level, as shown in
diagram.
(V
(V
X
(V
IN
IN
IN
Analog input differential
-V
-V
-V
INB
INB
INB
OL
) above maximum range
) below minimum range
) within range
) when the data stays within the range, or in a high-level state (V
amplitude
RHF1401 operating modes
IH
Table
Inputs
), all digital output buffers are in a high impedance state while the
12).
on
summarizes this functionality.
delay. This feature enables the chip select of the device.
Doc ID 13317 Rev 8
DFSB OEB
H
H
H
X
L
L
L
H
L
L
L
L
L
L
HZ
OR
H
H
H
H
L
L
(1)
IL
IH
), all digital outputs remain active. When
), DFSB provides standard binary
CLK D13
CLK D13 complemented
CLK D13
CLK D13 complemented
CLK D13
CLK D13 complemented
DR
HZ
IL
), the digital input DFSB provides
HZ (all digital outputs are in high
impedance)
Table
Most significant bit (MSB)
Outputs
14.
Figure 11: Timing
OH
) when the
RHF1401