PSD913G2 STMICROELECTRONICS [STMicroelectronics], PSD913G2 Datasheet - Page 5

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PSD913G2

Manufacturer Part Number
PSD913G2
Description
Configurable Memory System on a Chip for 8-Bit Microcontrollers
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
CNTL0,
CNTL1,
CNTL2
AD0 – AD15
PF0 – PF7
PG0 – PG7
*
Additional address lines can be brought into PSD via Port A, B, C, D, or F.
*
MCU BUS
PROG.
INTRF.
PORT
PROG.
PROG.
ADIO
PORT
PORT
PORT
PORT
G
F
INPUT
PLD
BUS
66
66
REGISTER
PAGE
CONFIG. &
SECURITY
GLOBAL
FLASH DECODE
FLASH ISP PLD
PLD ( DPLD )
(GPLD)
ALGORITHM
EMBEDDED
ADDRESS/DATA/CONTROL BUS
PLD, CONFIGURATION
& FLASH MEMORY
SECTOR
SELECTS
SECTOR
SELECTS
SRAM SELECT
CSIOP
I/O PORT PLD INPUT
LOADER
GPLD OUTPUT
GPLD OUTPUT
GPLD OUTPUT
RUNTIME CONTROL
AND I/O REGISTERS
CHANNEL
SERIAL
JTAG
256 KBIT SECONDARY
4 MBIT MAIN FLASH
FLASH MEMORY
(BOOT OR DATA)
64 KBIT BATTERY
BACKUP SRAM
4 SECTORS
8 SECTORS
MEMORY
PROG.
PROG.
PROG.
PROG.
PROG.
MANGMT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
PORT
POWER
A
B
UNIT
C
D
E
PA0 – PA7
PB0 – PB7
PC0 – PC7
PD0 – PD3
PE0 – PE7
VSTDBY
( PE6 )

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