M366S0823DTS SAMSUNG [Samsung semiconductor], M366S0823DTS Datasheet - Page 6

• Manufacturer Part Number: M366S0823DTS
• Description: PC100 Unbuffered DIMM(168pin) SPD Specification(64Mb D-die base)
• Manufacturer: SAMSUNG [Samsung semiconductor]

SERIAL PRESENCE DETECT
M374S0823DTS-C80/C1H/C1L
• Organization : 8Mx72
• Composition : 8Mx8 *9
• Used component part # : K4S640832D-TC80/C1H/C1L
• # of rows in module : 1 row
• # of banks in component : 4 banks
• Feature : 1,375mil height & single sided component
• Refresh : 4K/64ms
• Contents ;
Byte #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
0
1
2
3
4
5
6
7
8
9
# of bytes written into serial memory at module manufacturer
Total # of bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module
Data width of this assembly
...... Data width of this assembly
Voltage interface standard of this assembly
SDRAM cycle time @CAS latency of 3
SDRAM access time from clock @CAS latency of 3
DIMM configuration type
Refresh rate & type
Primary SDRAM width
Error checking SDRAM width
Minimum clock delay for back-to-back random column address
SDRAM device attributes : Burst lengths supported
SDRAM device attributes : # of
SDRAM device attributes : CAS latency
SDRAM device attributes : CS latency
SDRAM device attributes : Write latency
SDRAM module attributes
SDRAM device attributes : General
SDRAM cycle time @CAS latency of 2
SDRAM access time from clock @CAS latency of 2
SDRAM cycle time @CAS latency of 1
SDRAM access time from clock @CAS latency of 1
Minimum row precharge time (=t
Minimum row active to row active delay (t
Minimum RAS to CAS delay (=t
Minimum activate precharge time (=t
Module
Command and address signal input setup time
Command and address signal input hold time
Data signal input setup time
row
rows
density
on this assembly
Function Described
banks
RCD
RP
)
)
RAS
on SDRAM device
)
RRD
)
15.625us, support self refresh
precharge all, auto precharge
Non-buffered, non-registered
10ns
20ns
16ns
20ns
48ns
Burst Read Single bit Write
8ns
6ns
6ns
2ns
1ns
2ns
-80
+/- 10% voltage tolerance,
& redundant addressing
-
-
Function Supported
1, 2, 4, 8 & full page
256bytes (2K-bit)
1
t
CCD
row
128bytes
4
SDRAM
72 bits
LVTTL
0 CLK
0 CLK
1
10ns
banks
2 & 3
10ns
20ns
20ns
20ns
50ns
ECC
-1H
6ns
6ns
2ns
1ns
2ns
12
x8
x8
row
= 1CLK
of 64MB
9
-
-
-
PC100 Unbuffered DIMM
10ns
12ns
20ns
20ns
20ns
50ns
6ns
7ns
2ns
1ns
2ns
-1L
-
-
A0h
80h
60h
60h
00h
00h
14h
10h
14h
30h
20h
10h
20h
-80
Rev 0.1 Jan. 2000
Hex value
0Ch
A0h
0Eh
A0h
80h
08h
04h
09h
01h
48h
00h
01h
60h
02h
80h
08h
08h
01h
8Fh
04h
06h
01h
01h
00h
60h
00h
00h
14h
14h
14h
32h
10h
20h
10h
20h
-1H
A0h
C0h
60h
70h
00h
00h
14h
14h
14h
32h
20h
10h
20h
-1L
Note
1
1
2
2
2
2