M366S2953BTS-C7A SAMSUNG [Samsung semiconductor], M366S2953BTS-C7A Datasheet - Page 13

• Manufacturer Part Number: M366S2953BTS-C7A
• Description: SDRAM Unbuffered Module 168pin Unbuffered Module based on 512Mb B-die 62/72-bit Non ECC/ECC
• Manufacturer: SAMSUNG [Samsung semiconductor]

M366S2953BTS (128M x 64, 1GB Module)
(Recommended operating condition unless otherwise noted, T
(Recommended operating condition unless otherwise noted, T
DC CHARACTERISTICS
M374S6553ETS (64M x 72, 512MB Module)
Notes : 1. Measured with outputs open.
256MB, 512MB, 1GB Unbuffered DIMM
Operating current
(One bank active)
Precharge standby current
in power-down mode
Precharge standby current
in non power-down mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
Operating current
(Burst mode)
Refresh current
Self refresh current
Operating current
(One bank active)
Precharge standby current
in power-down mode
Precharge standby current
in non power-down mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
Operating current
(Burst mode)
Refresh current
Self refresh current
2. Refresh period is 64ms.
Parameter
Parameter
Symbol
Symbol
I
I
I
I
I
I
I
I
CC2
CC3
CC2
CC3
CC2
I
CC3
I
CC2
I
CC3
I
I
I
I
I
CC2
CC3
CC2
CC3
CC2
CC2
CC3
CC3
I
I
I
I
I
I
I
I
CC1
CC4
CC5
CC6
CC1
CC4
CC5
CC6
NS
NS
NS
NS
PS
PS
PS
PS
N
N
N
N
P
P
P
P
Burst length = 1
t
I
CKE ≤ V
CKE & CLK ≤ V
CKE ≥ V
Input signals are changed one time during 20ns
CKE ≥ V
Input signals are stable
CKE ≤ V
CKE & CLK ≤ V
CKE ≥ V
Input signals are changed one time during 20ns
CKE ≥ V
Input signals are stable
I
Page burst
4Banks activated
t
t
CKE ≤ 0.2V
Burst length = 1
t
I
CKE ≤ V
CKE & CLK ≤ V
CKE ≥ V
Input signals are changed one time during 20ns
CKE ≥ V
Input signals are stable
CKE ≤ V
CKE & CLK ≤ V
CKE ≥ V
Input signals are changed one time during 20ns
CKE ≥ V
Input signals are stable
I
Page burst
4Banks activated
t
t
CKE ≤ 0.2V
RC
O
O
CCD
RC
RC
O
O
CCD
RC
= 0 mA
= 0 mA
= 0 mA
= 0 mA
≥ t
≥ t
≥ t
≥ t
= 2CLKs
= 2CLKs
RC
RC
RC
RC
(min)
IL
IH
IH
IL
IH
IH
(min)
(min)
IL
IH
IH
IL
IH
IH
(min)
(max), t
(max), t
(max), t
(max), t
(min), CS ≥ V
(min), CLK ≤ V
(min), CS ≥ V
(min), CLK ≤ V
(min), CS ≥ V
(min), CLK ≤ V
(min), CS ≥ V
(min), CLK ≤ V
IL
IL
IL
IL
A
A
Test Condition
Test Condition
(max), t
(max), t
(max), t
(max), t
= 0 to 70°C)
CC
CC
= 0 to 70°C)
CC
CC
= 10ns
= 10ns
= 10ns
= 10ns
IH
IH
IH
IH
CC
CC
CC
CC
IL
IL
IL
IL
(min), t
(min), t
(min), t
(min), t
(max), t
(max), t
(max), t
(max), t
=∞
=∞
=∞
=∞
CC
CC
CC
CC
CC
CC
CC
CC
= 10ns
= 10ns
= 10ns
= 10ns
=∞
=∞
=∞
=∞
Rev. 1.1 February 2004
Version
Version
1,040
1,840
1,800
960
320
160
100
100
480
400
810
180
270
225
900
7A
7A
32
32
48
18
18
90
55
55
27
Unit
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
SDRAM
Note
Note
1
1
2
1
1
2