CYM1831PM-25C CYPRESS [Cypress Semiconductor], CYM1831PM-25C Datasheet - Page 3
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CYM1831PM-25C
Manufacturer Part Number
CYM1831PM-25C
Description
64K x 32 Static RAM Module
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CYM1831PM-25C.pdf
(8 pages)
AC Test Loads and Waveforms
Switching Characteristics
Document #: 38-05270 Rev. **
OUTPUT
READ CYCLE
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Note:
Parameter
Equivalent to:
RC
AA
OHA
ACS
DOE
LZOE
HZOE
LZCS
HZCS
WC
SCS
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
3.
4.
5.
6.
INCLUDING
JIG AND
SCOPE
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
At any given temperature and voltage condition, t
t
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
OL
HZCS
5V
/I
OH
OUTPUT
and t
and 30-pF load capacitance.
30 pF
HZWE
Read Cycle Time
Address to Data Valid
Data Hold from
Address Change
CS LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE LOW to High Z
CS LOW to Low Z
CS HIGH to High Z
Write Cycle Time
CS LOW to Write End
Address Set-Up to
Write End
Address Hold from
Write End
Address Set-Up to
Write Start
WE Pulse Width
Data Set-Up to Write
End
Data Hold from Write
End
WE HIGH to Low Z
WE LOW to High Z
[6]
(a)
are specified with C
R1 481
THÉ VENIN EQUIVALENT
Description
167
R2
255
L
= 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured 500 mV from steady-state voltage.
[4]
[4, 5]
[5]
Over the Operating Range
OUTPUT
1.73V
INCLUDING
JIG AND
SCOPE
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
15
15
10
10
10
5V
1831-15
3
0
0
2
2
8
2
3
0
HZCS
5 pF
15
15
is less than t
8
8
6
7
(b)
R1 481
20
20
15
15
15
12
1831-20
3
0
0
2
2
2
3
0
LZCS
for any given device. These parameters are guaranteed by design and not 100% tested.
[3]
20
20
10
10
10
8
R2
255
25
25
20
20
20
15
1831-25
3
0
3
2
2
2
3
0
GND
3.0V
25
25
15
15
13
13
< 5 ns
30
30
25
25
25
15
1831-30
3
0
3
2
2
2
3
0
30
30
20
15
15
15
10%
90%
ALL INPUT PULSES
35
35
30
30
25
20
1831-35
3
0
3
2
2
2
3
0
35
35
20
20
20
20
45
45
40
40
30
20
1831-45
3
0
3
2
2
2
3
0
CYM1831
Page 3 of 8
45
45
30
20
20
20
90%
10%
< 5 ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns