K9F4G08U0A SAMSUNG [Samsung semiconductor], K9F4G08U0A Datasheet - Page 37

• Manufacturer Part Number: K9F4G08U0A
• Description: FLASH MEMORY
• Manufacturer: SAMSUNG [Samsung semiconductor]

R/B
I/O
Figure 15. Two-Plane Block Erase Operation
K9K8G08U1A
K9F4G08U0A
Data
Input
R/B
I/O
Figure 14. Two-Plane Page Program
Two-Plane Block Erase
Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by
three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane.
The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/
Busy status bit (I/O 6).
X
0 ~ 7
NOTE :1. It is noticeable that same row address except for A
60h
2. Any command between 11h and 81h is prohibited except 70h and FFh.
80h
80h
A
A
A
12
18
19
Address (3 Cycle)
~ A
~ A
Address & Data Input
A
A
A
A
0
12
18
19
17 :
29 :
Block 4092
Block 4094
~ A
(2048 Block)
~ A
~ A
:
Fixed ’Low’
Fixed ’Low’
Fixed ’Low’
Block 0
Block 2
Plane 0
11 :
17 :
29 :
:
Fixed ’Low’
Fixed ’Low’
Fixed ’Low’
Valid
60h
11h
11h
A
A
A
Address (3 Cycle)
12
18
19
81h
~ A
~ A
Note*
t
DBSY
17 :
29 :
18
:
2
is applied to the two blocks
Fixed ’High’
Fixed ’Low’
valid
Block 4093
Block 4095
(2048 Block)
37
81h
Block 1
Block 3
Plane 1
D0h
Address & Data Input
A
A
A
A
0
12
18
19
~ A
~ A
~ A
11 :
17 :
29 :
:
10h
Fixed ’High’
Valid
Valid
Valid
t
BERS
FLASH MEMORY
10h
70h
t
Preliminary
PROG
I/O0
Fail
"1"
"0"
70h
Pass