HYB514171BJ-50- SIEMENS [Siemens Semiconductor Group], HYB514171BJ-50- Datasheet - Page 9

• Manufacturer Part Number: HYB514171BJ-50-
• Description: 256k x 16-Bit Dynamic RAM
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Notes
1. All voltages are referenced to
2.
3.
4. Address can be changed once or less while RAS =
5. An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least
6. AC measurements assume
7.
8. Measured with a load equivalent to 2 TTL loads and 100 pF.
9. Operation within the
10.Operation within the
11.Either
12.
13.Either
14.Either
15.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
Semiconductor Group
I
I
or less during a page mode cycle
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8
RAS cycles are required.
V
are also measured between
a reference point only. If
controlled by
a reference point only. If
controlled by
are not referenced to output voltage levels.
sheet as electrical characteristics only. If
data out pin will remain open-circuit (high impedance) through the entire cycle; if
t
from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O
(at access time) is indeterminate.
leading edge in read-write cycles.
t
t
CWD
CC
CC1
OFF (MAX.)
WCS
IH (MIN.)
,
I
and
,
>
CC3
t
RWD
t
t
t
t
CWD (MIN.)
RCH
DZC
CDD
,
and
I
,
I
CC4
,
CC4
t
OEZ (MAX.)
or
t
or
or
CWD
V
depend on output loading. Specified values are obtained with the output open.
t
t
t
and
CAC
AA
t
t
IL (MAX.)
DZO
RRH
ODD
and
.
and
.
I
must be satisfied.
must be satisfied for a read cycle.
must be satisfied.
CC6
define the time at which the output achieves the open-circuit conditions and
t
t
t
AWD
t
are reference levels for measuring timing of input signals. Transition times
AWD
RCD (MAX.)
RAD (MAX.)
depend on cycle rate.
>
are not restrictive operating parameters. They are included in the data
t
t
RCD
RAD
t
AWD (MIN.)
t
V
T
V
IH
= 5 ns.
is greater than the specified
limit ensures that
is greater than the specified
limit ensures that
SS
and
.
, the cycle is a read-write cycle and I/O will contain data read
V
IL
.
t
WCS
9
>
t
t
t
RAC (MAX.)
RAC (MAX.)
WCS (MIN.)
V
IL
. In case of
, the cycle is an early write cycle and
can be met.
can be met.
t
t
RCD (MAX.)
RAD (MAX.)
HYB 514171BJ-50/-60
I
CC4
limit, then access time is
limit, then access time is
t
t
it can be changed once
RCD (MAX.)
RAD (MAX.)
256k
t
RWD
is specified as
is specified as
16 DRAM
1998-10-01
>
t
RWD (MIN.)
,