EDD12322GBH-6ETS-F ELPIDA [Elpida Memory], EDD12322GBH-6ETS-F Datasheet - Page 8

• Manufacturer Part Number: EDD12322GBH-6ETS-F
• Manufacturer: ELPIDA [Elpida Memory]

Parameter
DQS falling edge hold time from CK
DQS input high pulse width
DQS input low pulse width
Address and control input setup time
Address and control input hold time
Address and control input pulse width
Mode register set command cycle time
Active to Precharge command period
Active to Active/Auto-refresh command
period
Auto-refresh to Active/Auto-refresh
command period
Active to Read/Write delay
Precharge to active command period
Column address to column address
delay
Active to active command period
Write recovery time
Autoprecharge write recovery and
precharge time
Self-refresh exit period
Internal Write to Read command delay
Average periodic refresh interval
Notes: 1. On all AC measurements, we assume the test conditions shown in “Test conditions” and full driver
Preliminary Data Sheet E1530E20 (Ver. 2.0)
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
3. The timing reference level is VDDQ/2.
4. Output valid window is defined to be the period between two successive transition of data out signals.
5. tHZ is defined as DOUT transition delay from low-Z to high-Z at the end of read burst operation. The
6. tLZ is defined as DOUT transition delay from high-Z to low-Z at the beginning of read operation. This
7. The transition from low-Z to high-Z is defined to occur when the device output stops driving. A specific
8. tAC, tDQSCK, tHZ and tLZ are specified with 15pF bus loading conditio
9. Minimum 3 clocks of tDAL (= tWR + tRP) is required because it need minimum 2 clocks for tWR and
strength is assumed for the output load, that is both A6 and A5 of EMRS is set to be “L”.
transition is defined to occur when the signal level crossing VDDQ/2.
The signal transition is defined to occur when the signal level crossing VDDQ/2.
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
reference voltage to judge this transition is not given.
minimum 1 clock for tRP.
tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next
higher integer.
Symbol
tDSH
tDQSH
tDQSL
tIS
tIH
tIPW
tMRD
tRAS
tRC
tRFC
tRCD
tRP
tCCD
tRRD
tWR
tDAL
tSREX
tWTR
tREF
-6E
min.
0.2
0.35
0.35
1.1
1.1
2.7
2
42
67.5
80
18
18
1
12
15
—
120
2
—
8
max.
—
—
—
—
—
—
—
120000
—
—
—
—
—
—
—
—
—
—
15.6
-7F
min.
0.2
0.35
0.35
1.3
1.3
3.0
2
45
67.5
80
22.5
22.5
1
15
15
—
120
1
—
n.
EDD12322GBH-TS
max.
—
—
—
—
—
—
—
120000
—
—
—
—
—
—
—
—
—
—
15.6
Unit
tCK
ns
tCK
ns
ns
ns
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
tCK
ns
µs
Notes
3
3
3
9