KMM372F400CK SAMSUNG [Samsung semiconductor], KMM372F400CK Datasheet - Page 6

• Manufacturer Part Number: KMM372F400CK
• Description: 4M x 72 DRAM DIMM with ECC using 4Mx4, 4K 2K Refresh, 3.3V
• Manufacturer: SAMSUNG [Samsung semiconductor]

DRAM MODULE
NOTES
1.
2.
3.
4.
5.
6.
7.
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are Vih/Vil. V
reference levels for measuring timing of input signals. Transi-
tion times are measured between V
are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1TTL loads and 100pF.
Voh=2.0V and Vol=0.8V.
Operation within the
can be met.
If
access time is controlled exclusively by
Assumes that
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
V
t
parameter. They are included in the data sheet as electrical
characteristics only. If
write cycle and the data out pin will remain high impedance
for the duration of the cycle.
WCS
OL
t
RCD
.
,
t
RWD
is greater than the specified
,
t
RCD
t
t
CWD
RCD
(max) is specified as a reference point only.
and
t
RCD
t
RCD
t
WCS
(max).
t
AWD
(max) limit insures that
t
WCS
are non restrictive operating
(min) the cycle is an early
IH
IH
(min) and V
(min) and V
t
t
RCD
CAC
(max) limit, then
.
IL
IL
(max) and
t
(max) are
RAC
(max)
OH
or
13.
14.
10.
12.
11.
8.
9.
If
then the cycle is a read-write cycle and the data output will
contain data read from the selected address. If neither of the
above conditions are satisfied, the condition of the data out
is indeterminated.
Either
These parameters are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
Operation within the
can be met.
t
access time is controlled by
t
time at which the output achieves the open circuit condition
and are not referenced to output voltage level.
If RAS goes to high before CAS high going, the open circuit
condition of the output is achieved by CAS high going. If CAS
goes to high before RAS high going , the open circuit condi-
tion of the output is achieved by RAS high going.
t
The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
RAD
CEZ
ASC
t
CWD
(max),
t
is greater than the specified
CP
t
RCH
t
min
CWD
or
t
REZ
t
RAD
(min),
t
RRH
(max),
(max) is specified as reference point only. If
must be satisfied for a read cycle.
t
RWD
t
RAD
t
KMM372F400CK/CS
KMM372F410CK/CS
WEZ
(max) limit insures that
t
RWD
(max) and
t
AA
.
(min) and
t
RAD
t
OEZ
(max) limit, then
t
(max) define the
AWD
t
AWD
t
RAC
(min),
(max)