LV4904V SANYO [Sanyo Semicon Device], LV4904V Datasheet - Page 17

• Manufacturer Part Number: LV4904V
• Description: Digital Input Class-D Power Amplifier
• Manufacturer: SANYO [Sanyo Semicon Device]

5.4 Data read
5.5 Internal register initialization
6. I
7. I
By sending the data read command, the data held in the registers of the LV4904V can be read. To read the data, first the
address is sent using a dummy write cycle, and then operation is restarted. Next, after the device ID and read flag has
been sent in the read cycle, the LV4904V outputs the data of the address sent in the dummy write cycle to the SDA line.
The transmission side establishes the I
ACK is not returned, and the stop condition is sent to end communication.
The internal registers accessed at address FFh through the I
into these registers, the internal registers are reset to the initial values.
2
2
C Register Map
C Command List
Register
GAINR
GAINL
DATA
MISC
STAT
RST
Register
GAINR
GAINL
DATA
MISC
start
Address
1
start
FFh
00h
10h
20h
21h
30h
1
Address
10h
20h
21h
30h
Device ID
0
1
PSTPR
PSTPL
1
Dummy Write Cycle
D7
0
R/W ACK
0
LV4904V
[2:0]
[4:3]
[6:5]
[5:0]
[5:0]
Bit
[7]
[6]
[7]
[6]
[7]
[0]
[1]
[2]
[3]
0
R/W ACK
2
LV4904V
C bus-free state to prepare for data reception. After the data has been received,
MUTEBR
MUTEBL
Read Address
D6
Read Address
MCKFS_I
Signal Name
MCKFS_I
SRATE_I
MUTEBR
1
MUTEBL
Reserved
DFORM
NSORD
PSTPR
PSTPL
GAINR
IDPEN
MDIDX
GAINL
1
2
C [1:0]
Write Address=0xFF
2
1
2
LV4904V
C
C
D5
1
LV4904V
ACK
1
3-wire serial PCM input, format setting
3-wire serial PCM input, sampling rate setting
Master clock rate setting
0 (Fixed)
Channel 1 (L channel), gain setting
Channel 1 (L channel), mute setting
Channel 1 (L channel), output disable setting
Channel 2 (R channel), gain setting
Channel 2 (R channel), mute setting
Channel 2 (R channel), output disable setting
1 (Fixed)
Pulse operation control when muted
PWM modulation index setting
Noise shaper order setting
SOFTR [7: 0] (for initializing registers)
start
Last accessed address (read-only)
2
C bus are write-only registers. By writing the value of FFh
1
1
Device ID
D4
SRATE_I
1
LV4904V
ACK
1
2
R/W
C [1:0]
Pin Description
NSORD
LV4904V
1
ACK
Read Cycle
D3
1
Write Data=0xFF
GAINR [5:0]
GAINL [5:0]
1
Read Address
Read Data
1
LV4904V
MDIDX
1
D2
1
1
LV4904V
DFORM [2:0]
ACK
IDPEN
stop
stop
D1
No.A1963-17/25
00000
00000
Value
Initial
000
01
00
0
0
0
0
0
1
1
0
0
D0
1