LH53B16R00 SHARP [Sharp Electrionic Components], LH53B16R00 Datasheet

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LH53B16R00

Manufacturer Part Number
LH53B16R00
Description
CMOS 16M (1M x 16/512K x 32) MROM
Manufacturer
SHARP [Sharp Electrionic Components]
Datasheet
LH53B16R00
FEATURES
DESCRIPTION
(mask-programmable-read-only memory) organized as
1,048,576
(Double Word mode). It is fabricated using silicon-gate
CMOS process technology.
The LH53B16R00 is a 16M-bit CMOS mask ROM
Access time: 120 ns (MAX.)
Access time in page mode: 50 ns (MAX.)
Supply current:
TTL compatible I/O
Three-state outputs
Single +5 V power supply
Static operation
Package:
Others:
524,288
1,048,576
(Word mode: W = V
(Double Word mode: W = V
– Operating: 180 mA (MAX.)
– Standby: 300 A (MAX.)
70-pin, 500-mil SSOP
– Non programmable
– Not designed or rated as radiation
– hardened
– CMOS process (P type silicon
substrate)
16 bits (Word mode) or 524,288
32 bit organization
16 bit organization
IL
)
IH
)
32 bits
CMOS 16M (1M
PIN CONNECTIONS
NOTE: D
70-PIN SSOP
W pin is set to be LOW in word mode, and data output
(D
31
31
/A
GND
) when set to be HIGH in double word mode.
GND
GND
V
V
V
D
D
D
D
D
D
D
D
-1
A
A
A
A
D
D
D
D
D
D
A
Figure 1. Pin Connections
A
A
A
A
CC
CC
D
CC
A
A
A
A
D
22
17
23
10
16
18
19
20
21
12
11
pin becomes LSB address input (A
4
0
4
5
7
7
9
0
2
3
5
2
3
6
6
8
1
1
10
17
18
1
2
3
4
6
8
9
11
12
13
14
15
16
19
21
23
25
26
27
29
34
35
5
7
20
22
24
28
30
31
32
33
16/512K
64
69
70
68
67
66
62
59
57
56
54
53
50
49
48
46
44
43
40
36
65
63
60
58
55
52
47
45
42
39
38
37
61
51
41
GND
GND
NC
NC
NC
W
OE
CE
D
D
D
D
V
D
D
D
D
GND
NC
D
D
D
D
V
D
D
D
D
V
A
A
A
A
A
A
CC
31
15
30
14
CC
18
17
29
13
28
12
27
11
26
10
25
9
24
8
CC
16
15
14
13
/A
-1
(NOTE)
32) MROM
-1
) when the
TOP VIEW
53B16R00-1
1

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LH53B16R00 Summary of contents

Page 1

... Non programmable – Not designed or rated as radiation – hardened – CMOS process (P type silicon substrate) DESCRIPTION The LH53B16R00 is a 16M-bit CMOS mask ROM (mask-programmable-read-only memory) organized as 1,048,576 16 bits (Word mode) or 524,288 (Double Word mode fabricated using silicon-gate CMOS process technology. ...

Page 2

... CIRCUIT 2 MEMORY MATRIX (1,048,576 x 16) (524,288 x 32) COLUMN SELECTOR TIMING SENSE AMPLIFIER GENERATOR ADDRESS ADDRESS BUFFER BUFFER Figure 2. LH53B16R00 Block Diagram CMOS 16M (1M x 16/512K x 32) MROM ...

Page 3

... RATING UNIT -0.3 to +7 +70 C -65 to +150 + TYP. MAX. UNIT 5.0 5.5 V LH53B16R00 PIN NAME Chip enable input Output enable input Power pin (+5 V) Ground No connection SUPPLY CURRENT Standby ( Operating Operating Operating Operating 3 ...

Page 4

... LH53B16R00 DC ELECTRICAL CHARACTERISTICS (V PARAMETER SYMBOL Input ‘High’ voltage V IH Input ‘Low’ voltage V IL Output ‘High’ voltage V OH Output ‘Low’ voltage V OL Input leakage current | Output leakage current | Operating current I CC1 I SB1 Standby current I SB2 Input capacitance ...

Page 5

... Figure 3. Read Cycle t t APA APA (NOTE) (NOTE DATA DATA VALID VALID , have concluded. Figure 4. Page Mode Read Cycle LH53B16R00 t CHZ t OHZ t OH DATA VALID 53B16R00-3 t CHZ t OHZ DATA DATA VALID VALID 53B16R00-4 ...

Page 6

... MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT ORDERING INFORMATION LH53B16R00 N Device Type Package Example: LH53B16R00N (CMOS 16M ( 500K x 32) Mask-Programmable ROM, 70-pin, 500-mil SSOP) 6 CMOS 16M (1M x 16/512K x 32) MROM 0.15 [0.006 12.90 [0.508] 16.20 [0.638] 12.50 [0.492] 15.60 [0.614] 35 0.15 [0.006] 1 ...

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