LH540203D SHARP [Sharp Electrionic Components], LH540203D Datasheet - Page 6

• Manufacturer Part Number: LH540203D
• Description: CMOS 2048X9 ASYNCHRONOUS FIFO
• Manufacturer: SHARP [Sharp Electrionic Components]

LH540203
OPERATIONAL MODES (cont’d)
Depth Cascading
required number of LH540203s in depth-cascaded mode.
In this arrangement, the FIFOs are connected in a circular
fashion, with the Expansion Out output (XO) of each
device tied to the Expansion In input (XI) of the next
device. One FIFO in the cascade must be designated as
the ‘first-load’ device, by tying its First Load input (FL/RT)
to ground. All other devices must have their FL/RT inputs
tied HIGH. In this mode, W and R signals are shared by
all devices, while logic within each LH540203 controls the
steering of data. Only one LH540203 is enabled during
any given write cycle; thus, the common Data In inputs of
6
Depth cascading is implemented by configuring the
FULL
DATA IN
D
0
- D
RS
W
8
9
Figure 6. FIFO Depth Cascading (6144 9)
9
9
9
FF
RS
FF
RS
FF
RS
LH540203
LH540203
LH540203
XI
XI
XI
XO
XO
XO
all devices are tied together. Likewise, only one
LH540203 is enabled during any given read cycle; thus,
the common Data Out outputs of all devices are wire-
ORed together.
used to generate a composite Full Flag and a composite
Empty Flag, by ANDing the FF outputs of all LH540203
devices together and ANDing the EF outputs of all devices
together. Since FF and EF are assertive-LOW signals,
this ‘ANDing’ actually is implemented using an asser-
tive-HIGH physical OR gate. The Half-Full Flag and the
Retransmit function are not available in depth-cascaded
mode.
EF
EF
FL
EF
FL
In depth-cascaded mode, external logic should be
FL
9
Vcc
9
Vcc
9
CMOS 2048
9
9 Asynchronous FIFO
R
DATA OUT
Q
0
- Q
8
EMPTY
540203-19