MT4C4001JC-12/883C AUSTIN [Austin Semiconductor], MT4C4001JC-12/883C Datasheet - Page 12

• Manufacturer Part Number: MT4C4001JC-12/883C
• Description: 1 MEG x 4 DRAM Fast Page Mode DRAM
• Manufacturer: AUSTIN [Austin Semiconductor]

4 MEG POWER-UP AND REFRESH
CONSTRAINTS
incompatibilities compared to the previous generation
1 Meg DRAM. The incompatibilities involve refresh and
power-up. Understanding these incompatibilities and
providing for them will offer the designer and system user
greater compatibility between the 1 Meg and 4 Meg.
REFRESH
the CBR (CAS\-BEFORE-RAS\) REFRESH cycle. The CBR
for the 1 Meg specifies the WE\ pin as a “don’t care.” The 4
Meg, on the other hand, specifies the CBR REFRESH mode
with the WE\ pin held at a voltage HIGH level.
JEDEC specified test mode (WCBR).
MT4C4001J
Rev. 2.2 06/05
A CBR cycle with WE\ LOW will put the 4 Meg into the
The EIA/JEDEC 4 Meg DRAM introduces two potential
The most commonly used refresh mode of the 1 Meg is
COMPARISON OF 4 MEG TEST MODE AND WCBR TO 1 MEG CBR
Austin Semiconductor, Inc.
12
POWER-UP
another problem. The 1 Meg POWER-UP cycle requires a
100µs delay followed by any eight RAS\ cycles. The 4 Meg
POWER-UP is more restrictive in that eight RAS\-ONLY or
CBR REFRESH (WE\ held HIGH) cycles must be used. The
restriction is needed since the 4 Meg may power-up in the
JEDEC specified test mode and must exit out of the test mode.
The only way to exit the 4 Meg JEDEC test mode is with
either a RAS\-ONLY or a CBR REFRESH cycle
(WE\ held HIGH).
SUMMARY
1. The 1 Meg CBR REFRESH allows the WE\ pin to be “don’t
care” while the 4 Meg CBR requires WE\ to be HIGH.
2. The eight RAS\ wake-up cycles on the 1 Meg may be any
valid RAS\ cycle while the 4 Meg may only use RAS\-ONLY
or CBR REFRESH cycles (WE\ held HIGH).
The 4 Meg JEDEC test mode constraint may introduce
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT4C4001J
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