GS72116AJ-10 GSI [GSI Technology], GS72116AJ-10 Datasheet - Page 7

• Manufacturer Part Number: GS72116AJ-10
• Description: 128K x 16 2Mb Asynchronous SRAM
• Manufacturer: GSI [GSI Technology]

AC Characteristics
Read Cycle
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = V
Rev: 1.04a 10/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Byte disable to output in High Z (UB, LB)
Byte enable to output in low Z (UB, LB)
Output disable to output in High Z (OE)
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE)
Chip enable to output in low Z (CE)
Output enable to output valid (OE)
Byte enable access time (UB, LB)
Output hold from address change
Chip enable access time (CE)
Address access time
Read cycle time
Parameter
Address
Data Out
IL
, WE = V
IH
Symbol
t
, UB and, or LB = V
Previous Data
t
t
t
t
OHZ
BHZ
t
t
t
t
OLZ
BLZ
t
t
t
LZ
HZ
RC
AC
OE
OH
AA
AB
*
*
*
*
*
*
t
OH
Min
—
—
—
—
—
—
—
7
3
3
0
0
7/18
-7
Max
3.5
—
—
—
—
—
7
7
3
3
3
3
t
AA
IL
t
RC
Min
—
—
—
—
—
—
—
8
3
3
0
0
-8
Max
3.5
3.5
3.5
3.5
—
—
—
—
—
8
8
4
Data valid
Min
—
—
—
—
—
—
—
10
3
3
0
0
-10
Max
© 2001, Giga Semiconductor, Inc.
—
—
—
—
—
10
10
4
4
5
4
4
GS72116ATP/J/T/U
Min
12
—
—
—
—
—
—
—
3
3
0
0
-12
Max
—
—
—
—
—
12
12
5
5
6
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns