CR14_10 STMICROELECTRONICS [STMicroelectronics], CR14_10 Datasheet - Page 16
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CR14_10
Manufacturer Part Number
CR14_10
Description
ISO14443 type-B contactless coupler chip with anti-collision and CRC management
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.CR14_10.pdf
(47 pages)
CR14 I²C protocol description
4
Table 6.
4.1
16/47
CR14
Select
CR14 I²C protocol description
The CR14 is compatible with the I²C serial bus memory standard, which is a two-wire serial
interface that uses a bi-directional data bus and serial clock.
The CR14 has a pre-programmed, 4-bit identification code, ’1010’ (as shown in
that corresponds to the I²C bus definition. With this code and the three Chip Enable inputs
(E2, E1, E0) up to eight CR14 devices can be connected to the I²C bus, and selected
individually.
The CR14 behaves as a slave device in the I²C protocol, with all CR14 operations
synchronized to the serial clock.
I²C Read and Write operations are initiated by a START condition, generated by the bus
master.
The START condition is followed by the Device Select Code and by a Read/Write bit (R/W).
It is terminated by an acknowledge bit. The Device Select Code consists of seven bits (as
shown in
●
●
When data is written to the CR14, the device inserts an acknowledge bit (9th bit) after the
bus master’s 8-bit transmission.
When the bus master reads data, it also acknowledges the receipt of the data Byte by
inserting an acknowledge bit (9th bit).
Data transfers are terminated by a STOP condition after an ACK for Write, or after a NoACK
for Read.
The CR14 supports the I²C protocol, as summarized in
Any device that sends data on to the bus, is defined as a transmitter, and any device that
reads the data, as a receiver.
The device that controls the data transfer is known as the master, and the other, as the
slave. A data transfer can only be initiated by the master, which also provides the serial
clock for synchronization. The CR14 is always a slave device in all I²C communications. All
data are transmitted Most Significant Bit (MSB) first.
Device select code
I²C start condition
START is identified by a High-to-Low transition of the Serial Data line, SDA, while the Serial
Clock, SCL, is stable in the High state. A START condition must precede any data transfer
command.
the Device Code (first four bits)
plus three bits corresponding to the states of the three Chip Enable inputs, E2, E1 and
E0, respectively
b7
1
Table
6):
b6
0
Device code
b5
1
Doc ID 11922 Rev 2
b4
0
E2
b3
Figure
Chip enable
6.
E1
b2
E0
b1
Table
RW
RW
b0
6),
CR14