T5761 ATMEL [ATMEL Corporation], T5761 Datasheet - Page 8
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T5761
Manufacturer Part Number
T5761
Description
UHF ASK/FSK Receiver
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.T5761.pdf
(32 pages)
Available stocks
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Part Number
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IC_ACTIVE
T5760 T5761
Bit check
( Number of checked Bits: 3 )
Dem_out
Data_out (DATA)
8 (32)
NO
Receiving mode:
The receiver is turned on permanently and
passes the data stream to the connected mC.
It can be set to Sleep mode through an OFF
command via Pin DATA or POLLING/_ON.
Output level on Pin IC_ACTIVE => high
I
S
Sleep mode:
All circuits for signal processing are
disabled. Only XTO and Polling logic is
enabled.
Output level on Pin IC_ACTIVE => low
I
T
Start-up mode:
The signal processing circuits are enabled.
After the start-up time (T
are in stable condition and ready to receive.
Output level on Pin IC_ACTIVE => high
I
T
Bit-check mode:
The incomming data stream is analyzed. If
the timing indicates a valid transmitter
signal, the receiver is set to receiving mode.
Otherwise it is set to Sleep mode.
Output level on Pin IC_ACTIVE => high
I
T
S
S
S
Sleep
Startup
Bit-check
= I
= I
= I
= I
Son
Soff
Son
Son
= Sleep X
/
Start–up mode
T
Start–up
OFF command
Bit check
OK ?
Sleep
YES
Figure 9. Timing diagram for complete successful bit check
Startup
1024 T
Preliminary Information
) all circuits
Clk
Figure 8. Polling mode flow chart
1/2 Bit
1/2 Bit
Bit–check mode
T
Sleep:
X
T
T
T
Bit-check:
Bit–check
Clk
Startup
Sleep
1/2 Bit
:
:
:
Bit check ok
1/2 Bit
5-bit word defined by Sleep0 to
Depends on the result of the
bit check
If the bit check is ok, T
depends on the number of bits to be
checked (N
utilized data rate.
If the bit check fails, the average
time period for that check depends
on the selected baud-rate range and
on T
defined by Baud0 and Baud1 in the
OPMODE register.
Sleep4 in OPMODE register
Extension factor defined by
XSleep
according to table 9
Basic clock cycle defined by f
and Pin MODE
Is defined by the selected baud rate
range and T
is defined by Baud0 and Baud1 in
the OPMODE register.
Clk
1/2 Bit
Std
. The baud-rate range is
Bit-check
Clk
. The baud-rate range
1/2 Bit
) and on the
Bit-check
Receiving mode
Rev. A2, 19-Oct-00
XTO