MSP3410G Micronas, MSP3410G Datasheet
MSP3410G
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MSP3410G Summary of contents
Page 1
... MICRONAS Edition May 27, 2003 6251-476-1DS DATA SHEET MSP 34x0G Multistandard Sound Processor Family MICRONAS ...
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... Loudspeaker and Headphone Outputs 14 2.5.6. Subwoofer Output 15 2.5.7. Quasi-Peak Detector 15 2.5.8. Micronas BASS (MB) 15 2.5.8.1. Dynamic Amplification 15 2.5.8.2. Adding Harmonics 15 2.5.8.3. Micronas BASS Parameters 15 2.6. SCART Signal Routing 15 2.6.1. SCART DSP In and SCART Out Select 16 2.6.2. Stand-by Mode Bus Interface 16 2.8. ADR Bus Interface 16 2.9. Digital Control I/O Pins and Status Change Indication 16 2 ...
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... I C-Bus Characteristics 2 72 4.6.3.5. I S-Bus Characteristics 74 4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC 75 4.6.3.7. Sound IF Inputs 75 4.6.3.8. Power Supply Rejection 76 4.6.3.9. Analog Performance 79 4.6.3.10. Sound Standard Dependent Characteristics Micronas 2 C Subaddress 10 hex 2 C Subaddress 11 hex 2 C Subaddress 12 hex 2 C Subaddress 13 hex May 27, 2003; 6251-476-1DS MSP 34x0G 3 ...
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... Manual/Compatibility Mode: Description of DSP Read Registers 100 6.6.1. Stereo Detection Register for A2 Stereo Systems 100 6.6.2. DC Level Register 101 6.7. Demodulator Source Channels in Manual Mode 101 6.7.1. Terrestric Sound Standards 101 6.7.2. SAT Sound Standards 101 6.8. Exclusions of Audio Baseband Features 101 6.9. Compatibility Restrictions to MSP 34x0D 4 May 27, 2003; 6251-476-1DS DATA SHEET Micronas ...
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... Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellec- tual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products. Micronas May 27, 2003; 6251-476-1DS MSP 34x0G ...
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... Broadcast Television Systems Com- mittee (BTSC). The DBX noise reduction, or alterna- tively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard ...
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... FM Stereo (A2) Version MSP 3410G available NICAM and FM Stereo (A2) Version MSP 3420G available NTSC Version (A2 Korea, BTSC with Micronas Noise Reduction (MNR), Japanese EIA-J system) MSP 3440G available NTSC Version (A2 Korea, BTSC with DBX noise reduction, Japanese EIA-J system) MSP 3450G available ...
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... PAL UK, Hong Kong SECAM-East Slovak. Rep. PAL currently no broadcast SECAM-East Poland China, Hungary Europe Sat. PAL ASTRA NTSC Korea NTSC Japan NTSC, PAL USA, Argentina USA, Europe Loudspeaker Subwoofer Headphone 2 SCART1 SCART Outputs 2 SCART2 2 ADR I S2 ADR Decoder DRP 3510A Micronas ...
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Functional Description ANA_IN1 AGC FM/AM Deemphasis: A 50/75 s, J17 DEMODULATOR DBX/MNR (incl. Carrier Mute) D Panda1 Prescale (0E hex ANA_IN2+ Decoded ...
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... MTS/MPX signal. Detection and evaluation of the pilot carrier, detection and FM demodulation of the SAP subcarrier. Process- ing of DBX noise reduction or Micronas Noise Reduc- tion (MNR). Japan Stereo: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Demodulation and evaluation of the identification signal and FM demodulation of the (L R)-carrier ...
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... A/B” channel: Analog or digital mono sound, stereo if available. In case of bilingual broad- cast, it contains both languages A (left) and B (right). Micronas – “Stereo or A” channel: Analog or digital mono sound, stereo if available. In case of bilingual broad- cast, it contains language A (on left and right). ...
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... Stereo or B (source select: 3) (source select: 4) Mono Mono Stereo Stereo A B analog Mono analog Mono NICAM Mono NICAM Mono NICAM Stereo NICAM Stereo NICAM A NICAM B Mono Mono Stereo Stereo Mono Mono Stereo Stereo Mono SAP Mono SAP Mono Mono Stereo Stereo Micronas ...
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... MSP 34x0G. For information on how to obtain this license key from Micronas, please contact your Micro- nas sales representative. 2.5.3. Micronas VOICE Micronas VOICE was developed to add the following improvements to speech signals: – Increase speech signal over background noise to increase intelligibility in noisy environments – ...
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... The Micro- nas VOICE functionality must be enabled by writing a "license key" into the MSP 34x0G. For information on how to obtain this license key from Micronas, please contact your Micronas sales representative. 2.5.4. Automatic Volume Correction (AVC) Different sound sources (e.g. terrestrial channels, SAT channels, or SCART) fairly often do not have the same volume level ...
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... After the adaption the loudspeakers and the cabinet, further customizing of MB allows individual fine tuning of the sound. Micronas BASS is placed in the subwoofer path. For applications without a subwoofer, the enhanced bass signal can be added back onto the Left/Right channels (see Fig. 2–1 on page 9). MB combines two effects: dynamic amplification and adding harmonics ...
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... S-Slave mode at the same time. For proper performance, the MSP clock oscillator requires a 18.432 MHz crystal. Note that for the phase-locked modes (NICAM, I tighter tolerance are required. May 27, 2003; 6251-476-1DS DATA SHEET 2 C-bus. C bus interactions are reduced S-Slave), crystals with Micronas ...
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... RD_DEM 0001 0001 WR_DSP 0001 0010 RD_DSP 0001 0011 Micronas response time is about 0.3 ms. If the MSP cannot accept another byte of data (e.g. while servicing an internal interrupt), it holds the clock line I2C_CL low to force the transmitter into a wait state. The bus slave ...
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... ACK data-byte device high address May 27, 2003; 6251-476-1DS DATA SHEET Bits[14:0] 0 Bit Bit Internal hardware status: not of interest error occured 1 : internal error occured will be set; it must be ACK P low Wait ACK data-byte- ACK data-byte high low NAK P low 2 C command. Micronas NAK P ...
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... Stereo or A/B and Matrix to Stereo (transparent mode) More examples of typical application protocols are listed in Section 3.4. “Programming Tips” on page 43. Micronas 1 0 3.2. Start-Up Sequence: Power-Up and I After POWER-ON or RESET (see Fig. 4–24), the inactive state. All registers are in the Reset posi- ...
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... MUTE 2 2 S1, I S2] FM/AM SOUNDA 2 2 S1, I S2] FM/AM SOUNDA 2 2 S1, I S2] FM/AM SOUNDA 2 2 S1, I S2] FM/AM SOUNDA 2 2 S1, I S2] FM/AM SOUNDA 00 hex 00 hex NO_MAT 00 hex 10 hex 00 hex ... 7F ] 00/00 hex hex See Page Micronas ...
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... Hz ... 400 Hz] [7:4] [sharp, medium, soft, very soft] [3:0] [off, on, Micronas BASS to Main [15:8] [0...100 / 100% and 100 / 0...100%] [ 127... and 0 / 128...0 dB]] [7:0] [Linear mode / logarithmic mode [15: ... 12 dB [15: ... 12 dB] ...
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... FF ] hex hex [7:0] [00 ... FF ] hex hex 00 1F [15:8] [00 ... FF ] hex hex [7:0] [00 ... FF ] hex hex May 27, 2003; 6251-476-1DS DATA SHEET See Page Micronas ...
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... In case of Automatic Sound Select, the B/G-codes case of Automatic Sound Select, the D/K-codes 4 3) HDEV3: Max. FM deviation must not exceed 540 kHz 4) HDEV2: Max. FM deviation must not exceed 360 kHz Micronas Automatic Standard Detection Standard Selection not detectable by Automatic ...
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... MSP-version, it detects and switches to the ana- log mono sound of this standard. Example: The MSPs 3420G and 3440G will detect a B/G-NICAM signal as standard 3 and will switch to the analog FM- Mono sound. May 27, 2003; 6251-476-1DS DATA SHEET However, the following method , the Automatic Standard hex Micronas ...
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... M-Korea 0002 (if MODUS[14,13]=00) hex M-Japan M-BTSC 0020 (if MODUS[14,13]=01) hex 0030 (if MODUS[14,13]=10) hex L-AM 0009 (if MODUS[12]=0) hex D/K1 D/K2 0004 (if MODUS[12]=1) hex D/K3 L-NICAM 0009 (if MODUS[12]=0) hex D/K-NICAM 000B (if MODUS[12]=1) hex Automatic Standard >07FF hex Detection still active Micronas hex May 27, 2003; 6251-476-1DS MSP 34x0G 25 ...
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... D_CTR_I/O_0 and _1 are input pins (level can be read out of STATUS[4,3]) undefined, must be 0 disable/enable STATUS change indication by means of the digital I/O pin D_CTR_I/O_1 Necessary condition: MODUS[ (active) off/on: Automatic Sound Select May 27, 2003; 6251-476-1DS DATA SHEET Name STANDARD_SEL MODUS 1) 1) Micronas ...
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... Address CONFIGURATION Register hex bit[15:1] 0 bit[ Micronas , continued hex not used, must be set to “0” 2 I2S_CL frequency and I S data sample length for master mode bit (1.024 MHz bit (2.048 MHz) May 27, 2003; 6251-476-1DS MSP 34x0G ...
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... I/O pin D_CTR_I/O_1 low/high level of digital I/O pin D_CTR_I/O_0 detected secondary carrier (2nd A2 or SAP sub-carrier) no secondary carrier detected detected primary carrier (Mono or MPX carrier) no primary carrier detected undefined May 27, 2003; 6251-476-1DS DATA SHEET Name STANDARD_RES STATUS Micronas ...
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... Satellite FM with adaptive deemphasis bit[15:8] 10 hex AM mode (MSP Standard Code = 9) bit[15:8] 7C hex Micronas hex hex Defines the input prescale gain for the demodulated signal off (RESET condition) 28 kHz FM deviation 50 kHz FM deviation 75 kHz FM deviation 100 kHz FM deviation 150 kHz FM deviation ...
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... V input leads to digital full scale) RMS 14 dB gain (400 mV input leads to digital full scale) RMS May 27, 2003; 6251-476-1DS DATA SHEET Name FM_MATRIX 2 C transmis- PRE_NICAM PRE_I2S1 PRE_I2S2 PRE_SCART Micronas ...
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... Section 6.5.1. on page 99) In Automatic Sound Select mode, the demodulator source channels are set according to Table 2–2. Therefore, the matrix modes of the corresponding out- put channels should be set to “Stereo” (transparent). Micronas , continued hex “FM/AM”: demodulated mono signal “ ...
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... If the clipping mode is “dynamic”, volume is reduced automatically if the signal amplitudes would exceed 2 dBFS within the IC. For operation of Micronas BASS, dynamic mode must be switched on continued ...
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... Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. Micronas , continued hex AVC off (and reset internal variables) AVC on 8 sec decay time 4 sec decay time 2 sec decay time 20 ms decay time (should be used for approx ...
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... May 27, 2003; 6251-476-1DS DATA SHEET Name TONE_MODE BASS_MAIN BASS_AUX Micronas ...
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... With positive equalizer settings, internal clipping may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore not recommended to set equalizer bands to a value that, in conjunction with vol- ume, would result in an overall positive gain. Micronas , continued hex 15 dB ...
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... Super Bass mode, the corner frequency is shifted up. The point of constant vol- ume is shifted from 1 kHz to 2 kHz continued hex 0.75 dB 0 normal (constant volume at 1 kHz) Super Bass (constant volume at 2 kHz) May 27, 2003; 6251-476-1DS DATA SHEET Name LOUD_MAIN LOUD_AUX Micronas ...
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... R), but a high-pass hex function for only signals. A value of 6 only signals, but a low-pass function for center signals. By using 8 quency response is automatically adapted to the sound material by choosing an optimal high-pass gain. Micronas , continued hex Enlargement 100% Enlargement 50% Enlargement 0.78% Effect off reduction 0 ...
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... E3 hex E2 hex ... 80 hex bit[7:0] 00 hex If Micronas BASS is added onto the main channel, this register should be set to 00 hex 00 2D Subwoofer Corner Frequency hex bit[15:8] 5...40 dec If Micronas BASS is active, SUBW_FREQ must be set to a value higher than the MB Lowpass Frequency (MB_LP). Choosing the corner frequency of the subwoofer closer to MB_LP results in a narrower MB frequency range ...
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... The Micronas BASS Amplitude Limit defines the maximum allowed amplitude at the output of the MB relative to 0 dbFS. If the amplitude exceeds MB_LIM, the gain of the MB is automatically reduced. Note that the Volume Clipping Mode must be set to “dynamic” (see page 32). ...
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... Mute (reset condition 0.125 dB increase in addition to the volume table 0.875 dB increase in addition to the volume table this must be 01 hex May 27, 2003; 6251-476-1DS DATA SHEET Name VOL_SCART1 VOL_SCART2 Micronas ...
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... Beeper Frequency 01 hex 40 hex FF hex Micronas , continued hex low/high of digital output pin D_CTR_I/O_1 (MODUS[3]=0) low/high of digital output pin D_CTR_I/O_0 (MODUS[3]=0) SCART1 to DSP input (RESET position) MONO to DSP input (set Sound A Mono in the channel matrix mode for the corresponding output channels) ...
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... MSP 34x0G - C12 MSP 34x1G - C12 MSP 3400G - C12 MSP 3410G - C12 MSP 3420G - C12 MSP 3440G - C12 MSP 3450G - C12 MSP 3460G - C12 MSP 34x0G - C12 May 27, 2003; 6251-476-1DS DATA SHEET Name QPEAK_L QPEAK_R corre- hex MSP_HARD MSP_REVISION MSP_PRODUCT MSP_ROM Micronas ...
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... Select the source channel and matrix for each out- put channel. 2. Set audio baseband processing. 3. Select volume for each output channel. Micronas 3.5. Examples of Minimum Initialization Codes Initialization of the MSP 34x0G according to these list- ings reproduces sound of the selected standard on the loudspeaker output. All numbers are hexadecimal. The ...
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... MSP 34x0G. The interrupt handler may adjust the TV display according to the new status information. Interrupt Handler: < <81 dd dd> // Read STATUS // adjust TV display with given status information // Return from Interrupt 44 , hex , hex hex 07FF change of the May 27, 2003; 6251-476-1DS DATA SHEET Micronas ...
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... Fig. 3–2: Software flow diagram for a Minimum demodulator setup for a European Multistandard TV set applying the Automatic Sound Select feature Micronas : @‘h€ƒyr for the essential bits: bdÃ2à ÃÃÃÃÃÃÃÃÃÃÃ6ˆ‡‚€h‡vpÃT‚ˆqÃTryrp‡Ã2 ...
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... MSP 34x0G 4. Specifications 4.1. Outline Dimensions Fig. 4–1: PSDIP64-1: Plastic Shrink Dual In-line Package, 64 leads, 750 mil Ordering code: PP Weight approximately 8. May 27, 2003; 6251-476-1DS DATA SHEET Micronas ...
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... Ordering code: PO Weight approximately 5. Micronas delivers two types of PSDIP52 packages (-1, -2). The packages have slightly different outline dimen- sions, but are considered identical. For logistics reasons, the customer cannot choose the package to be delivered. Micronas May 27, 2003; 6251-476-1DS MSP 34x0G ...
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... PSDIP52-2: Plastic Shrink Dual In-line Package, 52 leads, 600 mil 1) Ordering code: PO Weight approximately 5. Micronas delivers two types of PSDIP52 packages (-1, -2). The packages have slightly different outline dimen- sions, but are considered identical. For logistics reasons, the customer cannot choose the package to be delivered. 48 May 27, 2003; 6251-476-1DS DATA SHEET ...
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... DATA SHEET Fig. 4–4: PMQFP80-11: Plastic Metric Quad Flat Package, 80 leads, 14 Ordering code: QA Weight approximately 1.68 g Micronas high standoff May 27, 2003; 6251-476-1DS MSP 34x0G 49 ...
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... MSP 34x0G Fig. 4–5: PMQFP64-2: Plastic Metric Quad Flat Package, 64 leads, 10 Ordering code: QI Weight approximately 0 May 27, 2003; 6251-476-1DS DATA SHEET Micronas ...
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... Micronas Pin Name Type Connection (if not used I2C_CL IN/OUT OBL I2C_DA IN/OUT OBL I2S_CL IN/OUT LV I2S_WS IN/OUT LV I2S_DA_OUT OUT LV I2S_DA_IN1 IN LV ADR_DA OUT LV ADR_WS OUT ...
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... Analog reference voltage Not connected SCART 4 input, left SCART 4 input, right Analog Shield Ground SCART 3 input, left SCART 3 input, right Analog Shield Ground SCART 2 input, left SCART 2 input, right Analog Shield Ground SCART 1 input, left SCART 1 input, right Reference voltage IF A/D converter Micronas ...
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... Micronas Pin Name Type Connection (if not used MONO_IN IN LV AVSS OBL AVSS OBL AVSUP OBL AVSUP OBL ANA_IN1 ANA_IN IN AVSS via ANA_IN2+ ...
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... SCART outputs. Pins 36, 37, SC1_OUT_R/L – SCART1 Outputs (Fig. 4–21) Output of the SCART1 signal. Connections to these pins must use a 100- series resistor and are intended to be AC-coupled. May 27, 2003; 6251-476-1DS DATA SHEET Micronas ...
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... Analog input connection must be AC-coupled. Pin 52, ASG – Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Micronas Pins 53, 54, SC2_IN_L/R – SCART2 Inputs (Fig. 4–13) The analog input signal for SCART2 is fed to this pin. ...
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... DVSUP and DVSS pins. The ASG pins should be connected as closely as pos- sible to the MSP ground. If they are lead with the SCART-inputs as shielding lines, they should not be connected to ground at the SCART connector. 56 output signal ), to hex ). hex May 27, 2003; 6251-476-1DS DATA SHEET Micronas ...
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... CAPL_M DACA_L 26 39 AHVSUP VREF2 27 38 CAPL_A DACM_R 28 37 SC1_OUT_L DACM_L 29 36 SC1_OUT_R VREF1 DACM_SUB 31 34 SC2_OUT_L SC2_OUT_R Fig. 4–6: PSDIP64-1 package Micronas TP 1 AUD_CL_OUT 2 D_CTR_I/O_1 3 D_CTR_I/O_0 4 ADR_SEL 5 STANDBYQ 6 I2C_CL 7 I2C_DA 8 I2S_CL 9 I2S_WS 10 I2S_DA_OUT 11 I2S_DA_IN1 12 ADR_DA 13 ADR_WS 14 ADR_CL 15 DVSUP ...
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... ASG SC4_IN_R SC4_IN_L NC AGNDC AHVSS MSP 34x0G RESETQ I2S_DA_IN2 DVSS DVSS DVSS DVSUP DVSUP May 27, 2003; 6251-476-1DS DATA SHEET AHVSS CAPL_M 39 AHVSUP 38 CAPL_A 37 SC1_OUT_L 36 SC1_OUT_R 35 VREF1 34 SC2_OUT_L 33 SC2_OUT_R DACM_SUB DACM_L 27 DACM_R 26 VREF2 25 DACA_L DACA_R NC NC Micronas ...
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... NC 59 D_CTR_I/OUT1 60 D_CTR_I/OUT0 61 ADR_SEL 62 STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS Fig. 4–9: PMQFP64-2 package Micronas ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L AGNDC AHVSS 32 CAPL_M 31 AHVSUP 30 CAPL_A 29 SC1_OUT_L 28 SC1_OUT_R 27 VREF1 26 SC2_OUT_L 25 SC2_OUT_R DACM_SUB ...
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... Fig. 4–16: Input Pin: ADR_SEL N GND Fig. 4–17: Input/Output Pins: I2C_CL, I2C_DA DVSUP P N GND Fig. 4–18: Input/Output Pins: I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0 Fig. 4–19: Input/Output Pins: A XTAL_IN, XTAL_OUT, AUD_CL_OUT D May 27, 2003; 6251-476-1DS DATA SHEET DVSUP GND P 500 k N 2.5 V Micronas ...
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... DACA_R/L, DACM_R/L, DACM_SUB 26 pF 120 k 300 3.75 V Fig. 4–21: Output Pins: SC_2_OUT_R/L, SC_1_OUT_R/L DVSUP P N GND Fig. 4–22: Output Pins: I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL 0...2 V Fig. 4–23: Capacitor Pins: CAPL_A, CAPL_M 125 k 3.75 V Fig. 4–24: Pin: AGNDC Micronas May 27, 2003; 6251-476-1DS MSP 34x0G 61 ...
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... Measured on standard board according to JESD 51 Standard with maximum power consumption allowed for this package except where noted. SS Pin Name Min AHVSUP 0.3 DVSUP 0.3 AVSUP 0.3 0.3 20 May 27, 2003; 6251-476-1DS DATA SHEET Limit Values Unit Max 100 125 C 1300 mW 1200 mW 1000 mW 930 mW 9.0 V 6 0.3 V SUP2 20 mA Micronas ...
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... SCART Outputs I Output Current, other pins Cana connected to capacitors 1) “n” means “1”, “2”, “3”, or “4”, 2) The analog outputs are short-circuit proof with respect to Supply Voltage 1 and ground. Micronas Pin Name 1) SCn_IN_s, MONO_IN 1) SCn_IN_s, MONO_IN 1) SCn_OUT_s ...
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... Operating Conditions must not be exceeded at worst case conditions of the application except where noted. SS Pin Name Min. AHVSUP 7.6 4.75 DVSUP 4.75 3.15 AVSUP 4.75 STANDBYQ, 1 DVSUP May 27, 2003; 6251-476-1DS DATA SHEET Limit Values Unit Typ. Max 100 8.0 8.7 V 5.0 5.25 V 5.0 5.25 V 3.3 3.45 V 5.0 5. Micronas ...
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... C Main/AUX Volume Capacitor VMA C Main/AUX Filter Capacitor FMA 1) “n” means “1”, “2”, “3”, or “4”, “s” means “L” or “R”, “p” means “M” or “A” Micronas Pin Name Min. AGNDC 20% 20% 1) SCn_IN_s 20% ...
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... VREFTOP 20% 20% ANA_IN1 , 0 ANA_IN2 , ANA_IN 0.1 0 May 27, 2003; 6251-476-1DS DATA SHEET Limit Values Unit Typ. Max 100 nF 9 MHz 10.7 MHz 0 0.45 0 180 kHz 360 kHz 540 kHz Micronas ...
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... AUD_CL_OUT-pin. Change the capacitor value until the free running frequency matches 18.432 MHz as closely as possible. The higher the capacity, the lower the resulting clock frequency. Note: To minimize adjustment tolerances for all MSP-generations strongly recommended to use the so- called MSP-XTAL-REF ICs (available in all packages) for the capacitor adjustment. Micronas Pin Name 1) XTAL_IN, ...
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... Max Vol. Main and Aux = Vol. Main and Aux = -30dB 17 mA Vol. Main and Aux = Vol. Main and Aux = - 7.7 mA STANDBYQ = low 5.1 mA MHz load = 0 0.2 mA SUP3 max Micronas ...
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... Digital Input Low Voltage DIGIL V Digital Input High Voltage DIGIH I Input Current Address Select Pin ADRSEL Digital Output Levels V Digital Output Low Voltage DCTROL V Digital Output High Voltage DCTROH Micronas Pin Name Limit Values Min. Typ. Max. STANDBYQ 0.2 D_CTR_I/O_0/1 0 ADR_SEL 0.2 ...
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... High-to-Low Threshold t/ms t/ms May 27, 2003; 6251-476-1DS DATA SHEET Unit Test Conditions V SUP2 V SUP2 DVSUP RESETQ Note: The reset should not reach high level before the oscillator has started. This requires a reset delay of >2 ms 0.45 x DVSUP means 2.25 Volt with DVSUP = 5.0 V Micronas ...
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... Falling Edge of Clock C-Data Output Setup Time I2COL2 before Rising Edge of Clock I2C_CL T I2C1 I2C_DA as input I2C_DA as output 2 Fig. 4–26 bus timing diagram Micronas Pin Name Limit Values Min. Typ. I2C_CL, I2C_DA 0.6 120 120 55 55 I2C_CL 500 500 ...
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... May 27, 2003; 6251-476-1DS DATA SHEET Unit Test Conditions V SUP2 V SUP2 < U < DVSUP INPUT I2SOL I2SOH kHz MHz I2S_CONFIG[ MHz I2S_CONFIG[ for details see Fig. 4–27 “I2S bus timing diagram” kHz MHz Micronas ...
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... Detail B I2S_DA_OUT R LSB L MSB 2 Data: MSB first slave Detail C 1/F I2S_CL T s_I2S I2S_WS as INPUT I2S_WS as OUTPUT 2 Fig. 4–27 bus timing diagram Micronas 1/F I2SWS Detail C L LSB R MSB L LSB R MSB 1/F I2SWS Detail C L LSB R MSB L LSB R MSB Detail A,B I2SCL I2S_CL ...
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... I = 0.1 mA signal kHz RMS signal V RMS kHz 0.1 mA signal kHz signal dB with resp kHz Bandwidth 20000 kHz RMS signal Volume Full Scale input from RMS Micronas ...
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... From Analog Input to SCART Output 2 From I S Input to SCART Output 2 From I S Input to MAIN or AUX Output 1) “n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; Micronas Pin Name Limit Values Min. Typ. Max. 1) DACp_s 2.1 3.3 4.6 2.1 5 ...
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... Input Level = 3 dBr with resp kHz, AICL sig unweighted 20 Hz...16 kHz % Input Level = 3 dBr kHz, sig unweighted 20 Hz...20 kHz % Input Level = 3 dBr kHz, sig unweighted 20 Hz...16 kHz % Input Level = 3 dBr kHz, sig unweighted 20 Hz...16 kHz Micronas ...
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... I S Input to SCART Output 2 from I S Input to Main or AUX Out- put 1) “n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; Micronas Pin Name Limit Values Min. Typ. Max. MONO_IN SCn_IN_s ...
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... Hz...20 kHz) same signal source on left and right disturbing chan- nel, effect on each observed output channel dB SCART output load resis- tance SCART output load resis- tance Micronas ...
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... AM(2) measurement condition: QP/CCIR THD Total Harmonic Distortion Demodulated Signal fR AM Frequency Response AM 50...12000 Hz 1) “n” means “1” or “2”; “s” means “L” or “R”; Micronas Pin Name Limit Values Min. Typ. DACp_s 1.5 1 SCn_OUT_s 72 Noise 1 DACp_s, 1 ...
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... Bandpass 1 kHz 1%...66% EIM , DBX 300 Hz 3.1 kHz 14% Modulation, MNR 4.5 MHz carrier modulated with f = 15.734 kHz h kHz SIF level = 100 mV pp indication: STATUS Bit[6] kHz kHz standard BTSC stereo sig- nal, sound carrier only Micronas ...
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... EIM refers to 75- s Equivalent Input Modulation defined as the audio-signal level which results in a stated percentage modulation, when the DBX encoding process is replaced by a 75- s preemphasis network. Micronas Pin Name Limit Values Min. Typ. ...
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... 100% modulation deemphasis, Bandpass 1 kHz EIA-J Stereo Signal 100% modulation kHz 100% modula- tion deemphasis, RMS % unweighted kHz 1%...100% modula- tion deemphasis 0 kHz standard FM radio stereo signal Micronas ...
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... Table 5–2: Summary of NICAM 728 sound coding characteristics Characteristics Audio sampling frequency Number of channels Initial resolution Companding characteristics Coding for compressed samples Preemphasis Audio overload level Micronas B/G L 5.85 MHz 5.85 MHz 728 kbit/s Differentially encoded quadrature phase shift keying (DQPSK) by means of Roll-off filters 0.4 ...
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... R)/2 (L R)/2 language A May 27, 2003; 6251-476-1DS DATA SHEET Sound Carrier FM2 B/G D/K M 5.7421875 6.2578125 4.724212 6.7421875 5.7421875 kHz 15 25 kHz mono R (L R)/2 language B 54.6875 kHz 55.0699 kHz 2.5 kHz AM / 50% mono: unmodulated stereo: 117.5 Hz 149.9 Hz dual: 274.1 Hz 276.0 Hz Micronas ...
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... Table 5–5: Key parameters for Japanese FM-Stereo Sound System EIA-J Carrier frequency (f = 15.734 kHz) h Sound bandwidth Preemphasis Max. deviation portion to Aural Carrier Max. Freq. Deviation of Subcarrier Modulation Type Transmitter-sided delay Mono transmission Stereo transmission Bilingual transmission Micronas Aural BTSC-MPX-Components Carrier (L R) Pilot 4.5 MHz Baseband ...
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... Mono/Stereo/Bilingual Mono/Stereo/Bilingual Mono/Stereo/Bilingual Aural FM-Radio-MPX-Components Carrier (L R) Pilot 10.7 MHz Baseband kHz 90% 10% (100%) May 27, 2003; 6251-476-1DS DATA SHEET Bandwidth Deemphasis 15 kHz kHz adaptive 15 kHz adaptive 15 kHz adaptive (L R) RDS/ARI 0. 90% 5% Micronas ...
Page 87
... DCO2_HI 00 AB PLL_CAPS 00 1F Note: All registers except AUTO_FM/AM, A2_Threshold, and CM_Threshold are initialized during STANDARD SELECTION and are automatically updated when Automatic Sound Select (MODUS[0]=1) is on. Micronas where the ; these registers are not readable! hex Description 1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of ...
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... May 27, 2003; 6251-476-1DS DATA SHEET Reset Mode 00 hex 50 s OFF B hex 8 bit two’s complement ] 16 bit two’s complement ] 16 bit two’s complement Page Page 100 100 99 Page 100 100 100 Micronas ...
Page 89
... Forced Analog Mono 1) The NICAM path may be assigned to “Stereo or A/B”, “Stereo or A”, or “Stereo or B” source channels (see Table 2–2 on page 12). Micronas 6.3.1.1. Function in Automatic Sound Select Mode The Automatic Sound Select feature (MODUS[0]=1) includes the procedure mentioned above. By default, the internal ERROR_RATE threshold is set to 700 – ...
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... May 27, 2003; 6251-476-1DS DATA SHEET Source Select: Input at NICAM Path always NICAM; Mute in case of no NICAM available NICAM or FM/AM, depending on ERROR_RATE always FM/AM Micronas ...
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... Carrier-Mute THRESHOLD Register hex Defines threshold for the carrier mute feature bit[15:0] 0000 ... 002A ... 07FF recommended range : 0014 Micronas . : A2 Threshold hex force Mono Identification hex default setting after reset hex minimum Threshold for stable detection hex ...03C0 hex hex ...
Page 92
... DRP 3510A data sheet May 27, 2003; 6251-476-1DS DATA SHEET Automatic setting by STANDARD SELECT Register 2-8, 0A-60 9 hex 0 0 101000 100011 Range of Input Signal at pin ANA_IN1 and ANA_IN2 0.10 1 (recommended: 0.10 0 0. norm conditions of FM/NICAM or pp Micronas ...
Page 93
... STANDARD SELECTION register. The register ‘MODE_REG’ contains the control bits determining the operation mode of the MSP 34x0G in the MSP 34x0D Manual/Compatibility Mode; Table 6– 12 explains all bit positions. Micronas Gain Input Level at pin ANA_IN1 and ANA_IN2 3.00 dB maximum input level 3. ...
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... May 27, 2003; 6251-476-1DS DATA SHEET Automatic setting by STANDARD SELECT Register not affected by STANDARD SELECT register Micronas ...
Page 95
... MSP-Ch1 (NICAM or FM2) and one for MSP-Ch2 (FM1 = FM-mono). In Table 6–14 several coefficient sets are proposed. Micronas To load the FIR-filters, the following data values are to be transferred LSB-bound in a 16-bit word. The loading sequences must be obeyed. To change a ...
Page 96
... DCO2_HI 00 AB hex hex DCO_HI/hex DCO_LO/hex 0500 0000 0514 0000 0528 0000 05BA 0AAA 05C5 0C71 05E7 01C7 0640 0000 0690 0000 frequency Auto- search FIR2 126 0 0 Micronas ...
Page 97
... The MSP mutes the NICAM output automatically and tries to synchro- nize again as long as MODE_REG[6] is set. The operation mode is coded by C4-C1 as shown in Table 6–16. Micronas Table 6–16: NICAM operation modes as defined by the EBU NICAM 728 specification C4 C3 ...
Page 98
... Level Readout FM1”. Therefore, the FM DC Notch must be switched 00 hex on, and the demodulator part must be switched back to FM-demodulation mode. H hex hex 14 hex 00 hex May 27, 2003; 6251-476-1DS DATA SHEET , and the FM DC notch (see section dec s or adaptive) can be switched Micronas ...
Page 99
... Volume Modes of SCART1/2 Outputs Volume Mode SCART1 00 07 Volume Mode SCART2 00 40 linear 0000 RESET logarithmic 0001 Micronas Linear Mode Volume SCART1 Volume SCART2 L hex OFF L hex L hex 0 dB gain (digital full scale (FS ...
Page 100
... H hex Reading (two’s complement) near zero positive value (ideal reception hex negative value (ideal reception: 80 hex hex hex [8000 ... 7FFF hex hex values are 16 bit two’s complement defining the transition time of the DC Level Micronas ] ...
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... SAT Sound Standards Table 6–18 shows the source channel assignment of the demodulated signals for SAT sound standards. Micronas 6.8. Exclusions of Audio Baseband Features In general, all functions can be switched independently. Two exceptions exist: 1. NICAM cannot be processed simultaneously with the FM2 channel ...
Page 102
... AUTO_FM: analog Mono NICAM Mono NICAM Stereo Left = NICAM A Right = NICAM B Mono Stereo Mono Stereo Mono Left = Mono Right = SAP Mono Stereo for SAT-Modes Stereo or A/B Stereo or A (source select: 1) (source select: 3) Mono Mono Stereo Stereo Left = A (FM1) A (FM1) Right = B (FM2) Micronas ...
Page 103
... If the attached coprocessor is one of the MSP family, the following schematics help to determine the phase relationship. SCART1 SCART2 SCART DSP SCART3 Input Select SCART4 MONO Fig. 7–1: Phase diagram of the MSP 34x0G Micronas S_IN1/2 I S_OUT SCART1-Ch. Audio Baseband Processing SCART2-Ch. MONO, SCART1...4 May 27, 2003 ...
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... May 27, 2003; 6251-476-1DS DATA SHEET 100 ANA_IN1/2+ Alternative circuit for 1 k SIF-inputs for more attenuation of video components LOUD SPEAKER HEAD PHONE 1 nF 100 100 100 100 AHVSS Micronas ...
Page 105
... The Automatic Sound Select (ASS) malfunction has been corrected. In the previous version, under cer- tain circumstances and depending on the baseband features used, e.g.: Micronas BASS, Virtual Sur- round Sound, Equalizer... etc., the Automatic Sound Select Feature (ASS) did not work correctly. ...
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... By this publication, Micronas GmbH does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. ...