LC898023KL SANYO [Sanyo Semicon Device], LC898023KL Datasheet - Page 12

• Manufacturer Part Number: LC898023KL
• Manufacturer: SANYO [Sanyo Semicon Device]

5. Spindle Speed Detection Pins
6. Audio Interface Pins
7. RF Amplifier Interface Pins
8. Write Strategy Pins
9. ATIP Decoder Related Pins
<Other Pins>
FG (input)
LOUT, ROUT (output)
LDON (output)
WRITE, SSP2/1, RAPC, WAPC, H11T0, LDH, ATEST3, 1, WDAT, NWDAT (I/O)
ATIPSYNC (output)
BIDATA, BICLK (I/O)
WOBBLE (input)
ACRCNG (output)
RESET (input)
TEST4 to TEST0 (input)
XTALCK0 (input), XTAL0 (output)
XTALCK1 (input), XTAL1 (output)
R, VCNT, PDO, R1, VCNT1, PD1, MDC1 (I/O)
SUBSYNC (output)
EFMG (output)
SHOCK (output)
Input for the speed monitor signal from the spindle driver.
Left and right channel audio signal outputs.
RF amplifier interface.
Write strategy signal connections.
ATIP synchronization detection signal. (For monitoring)
Input mode: Input of the biphase data and biphase clock when an external ATIP demodulator is used.
Output mode: Output of the biphase data and biphase clock when the internal ATIP demodulator is used. (For
monitoring)
Wobble signal is input when the internal ATIP demodulator is used.
Outputs the result of the ATIP decoder CRC check. (For monitoring)
The LC898023K reset input. A low level input resets the LC898023K.
This pin must be held low for at least 1 µs when power is first applied.
Test inputs. These pins must be connected to ground.
Drive these pins at 33.8688 MHz. This signal is used, without modification, as main clock for the CD-ROM encoder
and decoder blocks, including the DRAM interface.
Main clock for the SCSI block. The LC898023K is designed so that it can operate even when the ECC and SCSI
blocks are not synchronized. Providing a 20 MHz input to the XTALCK0 and XTALCK1 pins assures that correct,
synchronized transfer at 10 Mbyte/s (20 Mbyte/s for Ultra SCSI) can be achieved. The maximum frequency that can
be used is 20 MHz.
Since both edges of the clock signal are used by Ultra SCSI, the duty ratio must be correct. Add feedback resistors on
the XTALCK1 and XTAL1 pins and take other measures as required.
Clock reproduction PLL circuit pins.
Subcode SYNC output signal from the CIRC encoder during recording. (For monitoring)
Outputs a high level during recording.
Outputs a high level when a mechanical shock is detected.
LC898023KW, 898023KL
No. 6614-12/13