VP305 MITEL [Mitel Networks Corporation], VP305 Datasheet - Page 6

• Manufacturer Part Number: VP305
• Description: Satellite Channel Decoder
• Manufacturer: MITEL [Mitel Networks Corporation]

VP305/6
DRAFT - PRELIMINARY DATA
LIST OF TABLES.
Table 1. Decimation ratios...............................................................................................................11
Table 2. Viterbi decoder input format ..............................................................................................13
Table 3. Viterbi decoder code rate ..................................................................................................13
Table 4. De-interleaver data sequence ...........................................................................................17
Table 5a. BANK Register ................................................................................................................20
Table 5b. Register bank 0. BANK[5:3] = 0 ......................................................................................20
Table 5c. Register bank 1. BANK[5:3] = 8....................................................................................... 20
Table 5d. Register bank 2. BANK[5:3] = 16 ....................................................................................21
Table 5e. Register bank 3. BANK[5:3] = 24 ....................................................................................21
Table 5f. Register bank 4. BANK[5:3] = 32 .....................................................................................21
Table 5g. Register bank 5. BANK[5:3] = 40 ....................................................................................22
Table 5h. Register bank 6. BANK[5:3] = 48 ....................................................................................22
Table 5i. Register bank 7. BANK[5:3] = 56...................................................................................... 22
Table 6a. QPSK Register details.....................................................................................................23
Table 6b. FEC Register details .......................................................................................................24
Table 7. BANK address decodes for parallel mode ........................................................................25
Table 9. Viterbi bit error rate threshold............................................................................................49
Table 10. Number of correct bits in the sync byte. .........................................................................50
Table 11. Number of correct sync bytes to retain lock ....................................................................50
Table 12. Number of consecutive sync bytes to establish block lock..............................................51
Table 13. Number of incorrect sync bytes to lose lock....................................................................54
Table 14. Enable / disable circuit blocks .........................................................................................56
Table 15. I²C bus timing ..................................................................................................................65
Table 16. Parallel bus timing ...........................................................................................................67
Table 17. MPEG data output rates ..................................................................................................70
Table 18. Recommended operating conditions...............................................................................71
Table 19. DC Characteristics ..........................................................................................................72
Table 20. Pinout details...................................................................................................................76
Table 21. Alphabetical listing of the pinout......................................................................................77
Table 22. Numerical listing of the pinout .........................................................................................78
The duplication or disclosure of data contained on this sheet is subject to the restrictions
on the title page of this document.
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