HM17CM4096 ETC2 [List of Unclassifed Manufacturers], HM17CM4096 Datasheet - Page 51

• Manufacturer Part Number: HM17CM4096
• Description: 128XRGBX162 OUTPUT LCD DRIVER IC with built-in RAM
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Display start command set
Display signal output set
Display selection control
RAM data length
Electric
(lower)
Electric
(upper)
Address set for internal
address reading
Oscillator Rf control
discharge
RE register set
Window end X address set
(lower)
Window end X address set
(upper)
Window end Y address set
(lower)
Window end Y address set
(upper)
Line inversion start address
(lower)
Line inversion start address
(upper)
Line inversion end address
(lower)
Line inversion end address
(upper)
Line inversion control
Gradation palette setting
selection
PWM mode control
RE register set
INSTRUCTION TABLE (4)
Notice 1) * mark is Don’t Care
Notice 2) The commands that upper/lower register settings are demanded are effective at the point of commands input.
But electric volume is effective after upper and lower register setting.
INSTRUCTION
volume
volume
control
control
CODE(80 series I/F)
CS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RD WR RE2 RE1 RE0 D7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RE flag
0/1
0/1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0/1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
Register address
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
D6
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
D5 D4 D3
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0 SC3 SC2 SC1 SC0
1
0
1
0
1
0
1
0
1 TST RE2 RE1 RE0 RE flag set
0 EX3 EX2 EX1 EX0
1
0 EY3 EY2 EY1 EY0
1 EY7 EY6 EY5 EY4
0
1
0
1
0
1
0
1 TST RE2 RE1 RE0 RE flag set
PW
HS
PW
LS3 LS2 LS1 LS0
LS7 LS6 LS5 LS4
LE3 LE2 LE1 LE0
LE7 LE6 LE5 LE4
MS
W
M
Address for register
*
*
*
*
*
*
*
Control address
C25
PW
ABS CKS WLS
DV6 DV5 DV4
RF2 RF1 RF0 RF oscillator Rf selection
EX6 EX5 EX4
MA
D2
6
*
*
*
*
DV3
read
FDC
PW
MB
D1
BT
1
*
*
*
FDC
LRE
PW
HM17CM4096
SON
DIS
MC
D0
PS
V
2
Common driver scan start
set
Control of outputs status of CKL
CL FLM FR
0CKL CL FLM FR=”L”(default)
1CKL CL FLM FR=”H”
PWM variable 16 /fixed 8 gray
mode selection
C256 256
ON/OFF(default : OFF)
FDC boost clock control
HSW
access mode
ABS effective
selection
CKS oscillator selection
WLS RAM access length 8 /16 bit
Internal register read out
Cap.
discharge
X
window mode
Y
window mode
Start line address set under
line inversion mode
End line address set under
line inversion mode
BT: blink type set
LREV: line inversion ON/OFF
Upper/lower
palette
PWM mode selection
end
end
high speed write in at 8 bit
Of
function
address
address
DV2
VLCD V1 V4
color
12
8
gradation
bit
- 51 -
under
under
Mode
RAM
D