TP82510 InnovASIC Inc, TP82510 Datasheet - Page 14

• Manufacturer Part Number: TP82510
• Description: ASYNCHRONOUS SERIAL CONTROLLER
• Manufacturer: InnovASIC Inc

IA82510
ASYNCHRONOUS SERIAL CONTROLLER
6. Problem: Receiving streamed data has many framing errors at fast baud rates (divisor=6)
7. Problem: Difficulty starting oscillator with crystal.
8. Problem: Intermittent and temperature sensitive crystal oscillator operation when cycling
9. Problem: Auto-acknowledge of interrupts via writing of LSR does not work.
10. Problem: ICM Status Clear command does not clear LSR/RST overrun error
11. Problem: In semi-automatic/uLAN mode, the RX FIFO is only opened when an address
12. Problem: Device fails to reset interrupt signal in auto acknowledge mode when character is
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through bad modem lines.
Analysis: DPLL is not robust for RXD signal with more than 1/16 bit time of variation.
Workaround: None
Analysis: No internal feedback resistor between X1 and X2.
Workaround: Install external 1-10Mohm resistor
power.
Analysis: Strapping state elements apparently transparent latches instead of flip flops. If flip
flop powers up to wrong state, crystal oscillator is disabled while reset is active. OK after first
reset following power-up.
Workaround: None
Analysis: Writing LSR directly sets/resets bits 4 through 0. Also writing 0 to LSR(0) – RX
FIFO – clears the RX FIFO level as seen by FLR. Writing zero to any other LSR bits clears the
corresponding LSR/RST flag, but also corrupts the FIFO location the write pointer is set to,
then increments both the write and read pointers.
Workaround: Use other means to service interrupts, such as read of RST or RXD
Analysis: ICM Status Clear command should clear everything in RST/LSR, MSR, and TMST
except RST/LSR(0). Overrun error was missed.
Workaround: Use other means to service interrupts
character matches the ACR1 or ACR0 registers (like full auto mode).
Analysis: In semi-auto mode, the RX FIFO should open on any address character.
Workaround: None
read from RX FIFO.
Analysis: RD strobe is outside the CS enable, which is outside of the Intel datasheet, but
apparently still works in the Intel device. Such a bus cycle allows the read data out, but fails to
generate the necessary internal strobe to change pointers. The same problem is found on write
accesses.
Workaround: Force bus interface to bracket RD strobe inside the CS enable
2001
The End of Obsolescence
ENG211001219-01
Page 14 of 14
As of Production Ver. 01
Data Sheet
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