CXA1998 SONY [Sony Corporation], CXA1998 Datasheet - Page 18

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CXA1998

Manufacturer Part Number
CXA1998
Description
Recording/Playback Equalizer Amplifier
Manufacturer
SONY [Sony Corporation]
Datasheet
• The DATA signal is taken in at the rising edge of the CLK signal.
• The DATA signal is taken into the internal shift register when the LATCH signal is low. (Outputs (Pins 15 to 22)
• The internal shift register data is latched and output in parallel at the rising edge of the LATCH signal.
• The CLK signal of the 11th bit should fall after the LATCH signal rises.
• Reset is done when the XRESET pin is low. (asynchronous method)
2. 11-bit serial data interface
hold the previous value while the LATCH signal is low.)
(Internal shift register data is loaded while the LATCH signal is high.)
Outputs (Pins 15 to 22) are all high (open) during reset.
(Pin 26)
DATA
D10
D11
D1
D2
D3
D4
D5
D6
D7
D8
D9
XRESET
M2
M1
PL2
PL1
BPB
BPA
PB MUTE
AGC OFF
SPEED
DECK AB
REC MUTE
(Pin 25)
(Pin 26)
(Pin 24)
(Pin 27)
LATCH
DATA
CLK
Control signal
D1
D2
Output pin
D3
Pin 22
Pin 21
Pin 20
Pin 19
Pin 18
Pin 17
Pin 16
Pin 15
– 18 –
D4
D5
D6
AGC function stops
Low, normal speed
DECK A selected
D7
Input set at low
Low mute OFF
Low mute OFF
Output
D8
Low
Low
Low
Low
Low
Low
D9
D10
D11
AGC function operates
High (open) mute ON
DECK B selected
Input set at high
High (open) 1.7
High mute ON
High (OPEN)
High (OPEN)
High (OPEN)
High (OPEN)
High (OPEN)
High (OPEN)
CXA1998AQ

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