EM78P468NBQ EMC [ELAN Microelectronics Corp], EM78P468NBQ Datasheet - Page 22

• Manufacturer Part Number: EM78P468NBQ
• Description: 8-BIT Microcontroller
• Manufacturer: EMC [ELAN Microelectronics Corp]

EM78P468N
8-BIT Microcontroller
18 •
4.1.16
4.1.17
Bit 4 : Not used
Bit 3 (IROUTE) : Define the function of P5.7/IROUT pin.
Bit 2 (TCCE) : Define the function of P5.6/TCC pin.
Bit 1 (EINT1)
Bit 0
Thes
Bit 7
PORT8 input changes.
Bit 6 (LPWTF) : interru
Bit 5
Bit 4
Bit 3 (CNT1F) : interrupt flag of internal counter 1 underflow.
Bit 2 (INT1F ): ext
Bit 1
Bit 0
R1
Bit 7
0~R31
ICIF
e bits are set to “1” when interrupt occurs respectively.
IROUTE = “0” : for bi-directional general I/O pin.
IROUTE = “1” : for IR or PWM output pin, the contro
must be set to “0”
TCCE = “0” : for bi-directional general I/O pin.
T
m
EINT = “0” : for bi-directio al gene
EINT1 = “1” : for external interrupt pin of INT1, the
IOC50) must be set to “1”
EINT0 = “0” : for bi-directional general I/O pin.
EINT0 = “1” : for external interrupt pin of INT0, the control bit of P5.4 (bit 4 o
IOC50) must be s
(EINT0) : Define the function of P5.4/INT0 pin.
(ICIF) : PORT 6, PORT 8, input status changed interrupt flag. Set when P
(HPWTF) : interrupt flag of internal high-pulse width timer underflo
(CNT2F) : interrupt flag of internal counter 2 under-flow.
(INT0F) : external INT0 pin interrupt flag.
(TCIF) : TCC timer overflow interrupt flag. Set when TCC timer overflows
(Address: 0Fh)
CCE = “1” : for externa
RF/ISR (Interrupt Status Register)
Address: 10h~3Fh;R10~R3F (General Purpo
ust be set to “1”
F an
1
LPWTF
: Defin
Bit 6
d R20
ernal INT1 pin interrupt flag.
e th
~R3
HPWTF
et to “1”
pt flag of internal low-pulse width timer underflow.
e funct
Bit 5
F (Ban
ion of P5.5/INT1 pin.
l input pin of TCC, the control bit of P5.6 (bit 6 of IOC50)
ks 0
n
CNT2F
Bit 4
~3) ar
(This specification is subject to change without further notice)
e ge
ral
CNT1F
I/O pin.
Bit 3
neral p
Product Specification (V1.2) 03.15.2005
urp
INT1F
oses re
Bit 2
l bit of P5.7 (bit 7 of IOC50)
control bit of P5.5 (bit 5 of
gist
se Register)
INT0F
er.
Bit 1
w.
Bit 0
TCIF
.
ORT6,
f