HY5DU281622DLT HYNIX [Hynix Semiconductor], HY5DU281622DLT Datasheet - Page 31

• Manufacturer Part Number: HY5DU281622DLT
• Description: 128Mb-S DDR SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

5.
6.
7.
8.
9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS
11. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
15. tDAL = 2 clocks + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest
16. tCK is equal to the actual system clock cycle time.
17. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
Rev. 0.0 / Apr. 2003
the DQ and DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For
example, if slew rate 1 = 0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
Example: For DDR400(D4) at CL=3 and tCK = 5 ns,
tDAL = (15 ns / 5ns) + (18 ns / 5 ns) = (3.0) + (3.6)
tRAS - BL/2 x tCK.
consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern
device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).
effects and p-channel to n-channel variation of the output drivers.
flat below VREF +/-310mV for a duration of up to 2ns.
Signal transitions through the DC region must be monotonic.
integer.
Round up each non-integer to the next highest integer: = (3) + (4), tDAL = 7 clocks
These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
CK, /CK slew rates are >=1.0V/ns
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, are
guaranteed by design or tester correlation.
required for READ command to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
For other commands, time interval of tRFC+2~5ns is required after Self Refresh Exit command.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
(1/SlewRate1)-(1/SlewRate2)
I/O Input Level
+280
V/ns
+/-0.25
mV
0.5
0.4
0.3
+/- 0.5
ns/V
0
Delta tDS
Delta tDS
+100
+170
+50
ps
ps
Delta tDS
0
+100
+50
ps
0
Delta tDH
Delta tDH
+150
+75
+50
ps
ps
Delta tDH
0
+100
+50
ps
0
HY5DU28422D(L)T
HY5DU28822D(L)T
HY5DU281622D(L)T
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