FX629J CMLMICRO [CML Microcircuits], FX629J Datasheet - Page 2

• Manufacturer Part Number: FX629J
• Description: Delta Modulation Codec
• Manufacturer: CMLMICRO [CML Microcircuits]

Pin Number Function
FX629J
10
11
1
2
3
4
5
6
7
8
9
Xtal/Clock : Input to the clock oscillator inverter. A 1.024MHz Xtal input or externally
derived clock is injected here. See Clock Mode pins and Figure 3.
Xtal : Output of clock oscillator inverter. Xtal circuitry shown is in accordance with CML
application note D/XT/1 April 1986.
No connection
Encoder Data Clock : A logic I/O port. External encode clock input or internal data clock
output. Clock frequency is dependant upon clock mode 1, 2 inputs and Xtal frequency (see
Clock Mode pins).
Encoder Output : The encoder digital output, this is a three state output whose condition is
set by Data Enable and Powersave inputs as shown :
Encoder Force Idle : When this pin is a logical '0' the encoder is forced to an idle state and
the encoder digital output is 0101..., a perfect idle pattern. When this pin is a logical '1' the
encoder encodes as normal. Internal 1M
Data Enable : Data is made available at the encoder output pin by control of this input. See
Encoder Output pin. Internal 1M
No connection
Bias : Normally at V
C
Encoder Input : The analogue signal input. Internally biased at V
are required on this input. The source impedance should be less than 100 , output idle
channel noise levels will improve with an even lower source impedance. See Fig. 3.
V
SS
4
. Internally pulled to V
: Negative Supply.
DD
/2 bias, this pin requires to be externally decoupled by a capacitor,
SS
Data Enable
when "Powersave" is a logical '0'.
1
0
1
Pullup.
2
Pullup.
Powersave
1
1
0
Encoder Output
Enabled
High Z (o/c)
Vss
DD
/2, external components