HY5DU561622FLTP-4 HYNIX [Hynix Semiconductor], HY5DU561622FLTP-4 Datasheet - Page 16

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HY5DU561622FLTP-4

Manufacturer Part Number
HY5DU561622FLTP-4
Description
256M(16Mx16) DDR SDRAM
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
Rev. 1.1 / Mar. 2008
7.
8.
Power-Up Sequence
VDD
VDDQ
VTT
VREF
/CLK
CLK
CKE
CMD
DM
ADDR
A10
BA0, BA1
DQS
DQ'S
Issue 2 or more Auto Refresh commands.
Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
LVCMOS Low Level
tVTD
VDD and CK stable
Power UP
T=200usec
tIS tIH
NOP
Precharge All
PRE
tRP
EMRS Set
CODE
CODE
CODE
EMRS
tMRD
(with A8=H)
Reset DLL
MRS Set
CODE
CODE
CODE
MRS
tMRD
NOP
* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command
Precharge All
PRE
tRP
Auto Refresh
2 or more
AREF
tXSRD*
tRFC
(with A8=L)
MRS Set
CODE
CODE
CODE
MRS
1HY5DU561622FTP-5
HY5DU561622FTP-4
tMRD
Non-Read
Command
CODE
CODE
CODE
ACT
CODE
CODE
CODE
READ
RD
16

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