GMS81508B HYNIX [Hynix Semiconductor], GMS81508B Datasheet - Page 49
GMS81508B
Manufacturer Part Number
GMS81508B
Description
HYUNDAI MICRO ELECTRONICS 8-BIT SINGLE-CHIP MICROCONTROLLERS
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet
1.GMS81508B.pdf
(100 pages)
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GMS81508B/16B/24B
12. ANALOG DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 8-bit digital
value. The A/D module has eight analog inputs, which are
multiplexed into one sample and hold. The output of the
sample and hold is the input into the converter, which gen-
erates the result via successive approximation. The analog
supply voltage is connected to AV
of A/D module.
The A/D module has two registers which are the control
register ADCM and A/D result register ADR. The register
ADCM, shown in Figure 12-2, controls the operation of
the A/D converter module. The port pins can be configured
as analog inputs or digital I/O. To use analog inputs, I/O is
selected input mode by R6DD direction register.
Note: On the initial RESET, R60 port is selected as an an-
alog input by ADCM register. So it can not be used digital
input port. To use this port as a digital I/O port, change to
except “0” the value of ADCM. Finally all eight ports can not
be used as digital I/O port simultaneously. At least one port
must be in analog port.
46
R60/AN0
R61/AN1
R62/AN2
R63/AN3
R64/AN4
R65/AN5
R66/AN6
R67/AN7
AV
DD
000
001
010
011
100
101
110
111
ADS[2:0]
ADEN
“1”
“0”
DD
of ladder resistance
Sample & Hold
S/H
Figure 12-1 A/D Block Diagram
How to Use A/D Converter
The processing of conversion is start when the start bit
ADST is set to “1”. After one cycle, it is cleared by hard-
ware. The register ADR contains the results of the A/D
conversion. When the conversion is completed, the result
is loaded into the ADR, the A/D conversion status bit
ADSF is set to “1”, and the A/D interrupt flag AIF is set.
The block diagram of the A/D module is shown in Figure
12-1. The A/D status bit ADSF is set automatically when
A/D conversion is completed, cleared when A/D conver-
sion is in process. The conversion time takes maximum 20
uS (at f
A/D result register
APPROXIMATION
XIN
SUCCESSIVE
CIRCUIT
=8 MHz).
ADR
ADDRESS: E9
RESET VALUE: Undefined
HYUNDAI MicroElectronics
ADIF
DEC. 1999 Ver 1.04
H
A/D
INTERRUPT
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