CL-PS6700-VC-A CIRRUS [Cirrus Logic], CL-PS6700-VC-A Datasheet

Page 1

... CL-PS7111 can support up to two CL-PS6700 devices, which allows up to two PC Card sockets per system. Addresses and data are passed to the CL-PS6700 through 16 bits of the 32-bit Data bus (D[15:0]). The PC Card socket is effectively isolated by the CL-PS6700. Except for power and ground pins, the pins on the socket only connect to the rest of the system through the CL-PS6700 ...

Page 2

... If a word write is indicated, write data also appears in the fourth clock phase. For read transfers, the CL-PS6700 drives the bus with read data during the first one or two clocks of the data phase. This interface bus is also shared by other memory devices and up to one additional CL-PS6700 device ...

Page 3

... PIN DESCRIPTIONS................................................................................ 10 2.1 CL-PS7111-to-CL-PS6700 Interface Signals........................................................... 10 2.1.1 Address/Data Bus Signals ............................................................................ 10 2.1.2 Access Control Signals................................................................................. 12 2.1.3 Interrupt and Abort Signals........................................................................... 13 2.1.4 Clock, Reset, and Sleep Signals .................................................................. 13 2.2 PC Card Interface Signals........................................................................................ 14 2.2.1 Address and Data Signals ............................................................................ 14 2.2.2 Access Control Signals................................................................................. 14 2.2.3 Additional Control for I/O Signals.................................................................. 16 2.2.4 Card Detect and Battery Status Signals ....................................................... 16 2 ...

Page 4

... Bus Timing — System Bus ...................................................................................... 35 5.2 Bus Operations ........................................................................................................ 38 6. PACKAGE SPECIFICATIONS ................................................................. 43 7. ORDERING INFORMATION .................................................................... 44 BIT INDEX................................................................................................ 45 INDEX....................................................................................................... TABLE OF CONTENTS PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller November 1997 ...

Page 5

... CL-PS6700 Low-Power PC Card Controller CONVENTIONS This section presents conventions, used in this data book. Abbreviations and Acronyms Acronym or Definition Abbreviation CIS card information structure CMOS complementary metal-oxide semiconductor CPU central processing unit DC direct current DMA direct-memory access EPROM erasable/programmable read-only memory FIFO fi ...

Page 6

... Hexadecimal numbers are presented with all letters in uppercase and a lowercase h appended. For exam- ple, 14h and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text. For example, ‘11’ binary number. Numbers not indicated single quotation marks are decimal. ...

Page 7

... RESET_L [I] 1 PIRQ_L[0] [ PIRQ_L[1] [O] MD[0] [I/O] 4 MD[1] [I/O] 5 MD[2] [I/O] 6 VSS_O 7 MD[3][I/O] 8 V3V_O 9 MD[4] [I/O] 10 MD[5] [I/O] 11 V3V_CORE 12 MD[6] [I/O] 13 MD[7] [I/O] 14 VSS_CORE 15 PCLK [I] 16 MD[8] [I/O] 17 MD[9] [I/O] 18 MD[10] [I/O] 19 VSS_O 20 MD[11] [I/O] 21 V3V_O 22 MD[12] [I/O] 23 MD[13] [I/O] 24 MD[14] [I/ November 1997 PRELIMINARY DATA BOOK v1.0 CL-PS6700 100-Pin VQFP ...

Page 8

... Pin Listings Table 1-1 lists the pins of the CL-PS6700 in alphabetical order. Table 1-1. Alphabetical Listing Signal Pin Signal Type Name No. Name MD[0] 4 I/O PCM_A[7] MD[1] 5 I/O PCM_A[8] MD[2] 6 I/O PCM_A[9] MD[3] 8 I/O PCM_A[10] MD[4] 10 I/O PCM_A[11] MD[5] 11 I/O PCM_A[12] MD[6] 13 I/O PCM_A[13] MD[7] 14 I/O PCM_A[14] MD[8] 17 I/O PCM_A[15] MD[9] 18 I/O PCM_A[16] MD[10] 19 I/O PCM_A[17] MD[11] 21 I/O PCM_A[18] MD[12] 23 I/O PCM_A[19] MD[13] 24 I/O PCM_A[20] MD[14] 25 I/O PCM_A[21] MD[15] 26 I/O PCM_A[22] PCE_L 30 I PCM_A[23] PCLK 16 I PCM_A[24] ...

Page 9

... MD[2] I VSS_O – MD[3] I V3V_O – MD[4] I MD[5] I V3V_CORE – MD[6] I MD[7] I VSS_CORE – PCLK MD[8] I MD[9] I MD[10] I VSS_O – MD[11] I V3V_O – MD[12] I MD[13] I MD[14] I November 1997 PRELIMINARY DATA BOOK v1.0 ...

Page 10

... Address Phase Card address is a 26-bit byte address. The MD bus carries the upper 10 address bits, plus control bits during the first clock of Chip Enable (PCE_L low), and the remaining (lower) 16 address bits during the second clock. ...

Page 11

... For card reads, the data phase is deferred until card data has been collected as signaled by PRDY; the data phase is initiated by a second assertion of PCE_L, and the CL-PS6700 drives this bus with read data in the clock following the assertion of PCE_L (if a word read, during the second clock following PCE_L). ...

Page 12

... NOTE: PRDY should be pulled up with a 100-k resistor. PC Card ready: This signal goes to the CL-PS7111 and serves as both an address ready and data ready signal. It can also indicate a busy (card RDY/BUSY pin) status of the corresponding PC Card socket (see configuration bit “Include Card Ready in PRDY”). Normally, the CL-PS6700 leaves this signal asserted (high) ...

Page 13

... PCLK can be disabled when the PC Card subsystem is not in use. RESET_L I sys This reset signal can be driven by one of the GPIO outputs of the CL-PS7111 system reset active-low input and places all CL-PS6700 registers and outputs in their default power-up/reset condition. PSLEEP_L ...

Page 14

... DMA transfer, this signal is used as a terminal count and is asser ted along with PCM_IOWR_L during the last DMA card write PIN DESCRIPTIONS PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller November 1997 ...

Page 15

... Single-mode. This data wait signal is used by the card to delay completion of an in-progress memory or I/O access cycle sampled by the CL-PS6700 with a flip-flop clocked on the rising edge of PCLK, then fed to the card interface logic. In order to be recognized, this sig- nal must be asserted at least two clocks before the end of the command strobe. ...

Page 16

... I/O Mode: PCM_BVD[2] becomes SPKR_L, the Audio Digital Waveform signal, while PCM_BVD[1] becomes the STSCHG_L signal, a status line that indicates state changes of BVD, CD, and WP. The state of the BVD inputs can be read by the CPU in the CL-PS6700 Status registers and are also available on the PC Card registers. ...

Page 17

... V3V_O sys power plane (V3V_Core). V5V_O pcm Power to PC Card interface I/O buffers; either This pin should be tied to the highest voltage in the system (as seen by CL-PS6700; either 3.3 VDD_HI VDDhi V). VSS_Core Ground pins for the core and input buffers. VSS_O Ground pins for output buffers ...

Page 18

... Multifunction cards with both I/O and memory DMA-capable cards Each card can be 3 and power to each card is managed independently by the CL-PS7111 and the corresponding CL-PS6700. General-purpose digital I/O (PCM_VS pins on the CL-PS6700) can be used by the CPU to detect the voltage requirements of a card before applying power. ...

Page 19

... The CL-PS6700 can be programmed to assemble/disassemble the CL-PS7111 transfers to the width of the PC Card. The CL-PS6700 has read and write buffers, allowing posting of both reads and writes. The read queue is single entry, and the write FIFO can queue up to four CL-PS7111 transactions ( bytes) ...

Page 20

... Power States 3.2.1 Active State The Active State is the normal operating state entered whenever PC Card accesses are required. In this state the PCLK input is active, the PSLEEP_L input is deasserted, and the Idle bit in the Power Manage- ment register is cleared. 3.2.2 Idle State Normally, Idle State is entered/exited dynamically in hardware (by CL-PS6700 control logic) transparent to software ...

Page 21

... The upper 16 bits of register reads should be treated as undefined. The CL-PS6700 registers are accessible in all power states where the CL-PS6700 is powered and has a running PCLK (regardless of the state of PRDY). PC Card access should be done only when the CL-PS6700 is in Active mode. ...

Page 22

... NOTE: The three Reserved Interrupt registers must be written with all ones (32’hFFFFFFFF) before interrupts can be captured and output to the PIRQ[1:0] pins REGISTERS Default Input Level PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller R November 1997 ...

Page 23

... The Interrupt Status register indicates which interrupt inputs have transitioned (rising edge or falling edge) since they were last cleared (using the Interrupt Clear register). The OR’ing of bits in the Interrupt Status register (bits not masked by the Mask register) generates an interrupt on either the PIRQ[0]_L or PIRQ[1]_L output as selected in the Interrupt Output Select register. A bit set to ‘ ...

Page 24

... Auto Power Down Card on Standby. If this bit is set, the Card Power Enable bit (bit 5) is cleared when Standby mode is entered. 1 Idle. When this bit is set, it forces the CL-PS6700 into Low Power mode. Most internal clocks are stopped with the exception of register access. Idle mode has no affect on I/O pads or card power control. ...

Page 25

... PCTL[2:1] are bidirectional. The PCTL[2:1] input value is at the Interrupt Pins register and can generate an interrupt while PCTL[0] cannot generate an interrupt. 2:0 PCTL[2:0] Output Value When Card Power Enable Bit is High. NOTE: If Power Management register bit 7 is cleared, then this bit is a don’t care November 1997 PRELIMINARY DATA BOOK v1 ...

Page 26

... PC Cards are defined as little–endian, while the ARM CPU inside the CL-PS7111 can be big–endian or little–endian. 4 Transaction Queue Enable. When this bit is set, it enables queuing one or more CL-PS7111 write operations. If this bit is cleared, then PRDY goes low after a write until the write is com- plete. 3 Transaction Queue Threshold Control. ...

Page 27

... DMA Request Input Select. Selects input to be used for DMA handshake between the CL-PS6700 and the card. Currently, there is no dedicated card pin assigned for DMA request. 000 – Disable DMA access 001 – PCTL[2] 010 – PCM_VS[2] 011 – ...

Page 28

... Card Reset Output Enable. If this bit is set, PCM_RESET is driven with the value of bit 12. If this bit is cleared, the output is tristated. 10 Card Enable. This bit must be set for the CL-PS6700 to make a card access card access is attempted by the CL-PS7111 while this bit is cleared, a read time–out or WR_FAIL interrupt occurs. ...

Page 29

... Count Field for Address and Data Setup Time. Settings 3Fh correspond times the prescale value. The period starts at valid address and ends when the command strobe is active. The setup time equals ([Prescale setup PCLK November 1997 PRELIMINARY DATA BOOK v1.0 ) (0X0C003000 ...

Page 30

... Setup PCLK REGISTERS ) (0X0C003800 Count (0X0C003C00) Count constant Count constant PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller Default R/W 00 R/W 1Fh R/W 00 R/W 00h R/W Default R/W 00 R/W 00h R/W 00 R/W 00h R ...

Page 31

... PI Protected input; that is, the internal input buffer is de-coupled from the pin. N Normally operating input a Synchronous signal indicates whether a signal is synchronous to PCLK. b These indicate the state of each output signal or the input pin during various states of the device. For Reset, Table 4-2 on page 32 indicates the state of each signal when RESET_L is asserted and power sta- bilizes ...

Page 32

... PCTL[2:0] Prog. a The Idle mode is entered and exited by writing the register bit Idle . In Idle mode most internal clocks are gated off, and only the CL-PS6700 register access is supported. All CL-PS6700 inputs and outputs function normally. b The PCM_BVD[1] input protection can be disabled during Card power-off. ...

Page 33

... CL-PS6700 Low-Power PC Card Controller 5. ELECTRICAL SPECIFICATIONS Table 5-1. Absolute Maximum Ratings Description Ambient temperature under bias Storage temperature Voltage on any pin with respect to ground Operating power dissipation Standby state power dissipation Power supply voltage Injection current (latch up) NOTE: Stressing the device above those listed in Absolute Maximum Ratings may cause permanent damage to the component. These are stress ratings only. Functional operation at these or any conditions above those indi- cated in the operational sections of this specifi ...

Page 34

... 3.3 V, PCLK = Lithium backup PCLK = DC (stopped 5.0 V, PCLK = 18 MHz 5.0 V, PCLK = PCLK = 5.0 V, PCL = 18 MHz 5.0 V, PCLK = 5.0 V, PCLK = November 1997 OL OH < ...

Page 35

... MD bus address phase input hold bus data phase input setup bus data phase input hold 3d t PCLK high to MD bus output new data 3e t PCE_L to MD bus output driven 3f t PCLK high to MD bus output High PRDY input setup ...

Page 36

... PCM_CD_L high to card outputs 7f t PCM_D input setup 8a t PCM_D input hold 8b t PCLK low to PCM_D outputs 8c t PCLK low to PCM_D driven (following card read PCLK high to PCM_D High-Z (card read PCLK high to command strobes 9a t PCLK high to command strobes 9b t ...

Page 37

... PCLK high to PCM_RESET output 19a t PCLK high to PCM_RESET output driven 19b t PCLK high to PCM_RESET output High-Z 19c a Card outputs refer to PCM_A, PCM_REG_L, PCM_CE_L, PCM_OE_L, PCM_WE_L, PCM_IORD_L, and PCM_IOWR_L. b Command strobe refers to PCM_OE_L, PCM_WE_L, PCM_IORD_L, and PCM_IOWR_L. c Card inputs refer to PCM_CD_L, PCM_VS_L, PCM_BVD, PCM_WP, PCM_WAIT_L, and PCM_RDY. ...

Page 38

... ADDR PHASE DATA PHASE CYCLE 2 CYCLE ADDR Figure 5-1. Memory or Register Write ADDR PHASE DATA PHASE MD BUS CYCLE 2 TURN-AROUND ADDR. HI ADDR Figure 5-2. Register Read ...

Page 39

... CL-PS6700 Low-Power PC Card Controller Figure 5-3. System Bus: Card Data Read November 1997 PRELIMINARY DATA BOOK v1 ELECTRICAL SPECIFICATIONS 39 ...

Page 40

... Figure 5-4. PC Card Bus Read Operation ELECTRICAL SPECIFICATIONS PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller November 1997 ...

Page 41

... CL-PS6700 Low-Power PC Card Controller Figure 5-5. PC Card Bus Write Operation November 1997 PRELIMINARY DATA BOOK v1 ELECTRICAL SPECIFICATIONS 41 ...

Page 42

... ELECTRICAL SPECIFICATIONS DATA OUT 17a Figure 5-7. Standby Mode Timing PRELIMINARY DATA BOOK v1.0 CL-PS6700 Low-Power PC Card Controller 17b November 1997 ...

Page 43

... Before beginning any new design with this device, please contact Cirrus Logic for the latest package information November 1997 PRELIMINARY DATA BOOK v1.0 15.56 (0.613) 16.50 (0.650) 13.90 (0.547) 14.10 (0.555) CL-PS6700 100-Pin VQFP Pin 1 Indicator 0.30 (0.012) 0.70 (0.028 ...

Page 44

... ORDERING INFORMATION CL – PS6700 – VC – A Cirrus Logic Inc. Personal Systems Part number † Contact Cirrus Logic for up-to-date information on revisions ORDERING INFORMATION Temperature range Commercial Package type VQFP (very-tight-pitch plastic quad flat pack PRELIMINARY DATA BOOK v1 ...

Page 45

... E Enable Active pull-up on Open-Drain Interrupt Outputs PIRQ_L[1:0] 26 Enable Assembly and Disassembly 26 Enable Auto Idle Mode 24 Enable Handshake Using Card Rdy Signal 26 Enable Handshake with CL-PS7111 Using PDREQ_L 27 Endian Conversion Enable 26 G GPIO Direction 25 GPIO Output Value When Card Power Enable Bit is High 25 ...

Page 46

... PC Card Bus Read bus operation. See bus operations PC Card Bus Write bus operation. See bus operations pins alphabetical listing 8 description 10 diagram 7 ground and power 17 MD[15:0] 10 numerical listing 9 PCE_L 12 PCLK 14 PCM_ IOWR_L 16 PCM_A[25:0] 14 PCM_BVD[2:1] 16 PCM_CD_L[2:1] 16 PCM_CE_L[2:1] 14 PCM_D[15:0] 14 PCM_IORD_L 16 PCM_OE_L 14 PCM_RDY 15 PCM_REG_L 15 ...

Page 47

... Card Power Control 25 Device Information November 1997 PRELIMINARY DATA BOOK v1.0 registers (cont.) DMA control 27 Interrupt Clear 23 Interrupt Input Level 21 Interrupt Mask 23 Interrupt Output Select 23 Interrupt Status 23 Power Management 20 System Interface Configuration 26 S Standby Mode Timing bus operation. See bus operations System Bus Card Data Read bus operation ...

Page 48

... Cirrus Logic, Inc. Cirrus, Cirrus Logic, AccuPak, Alpine, Clear3D, Crystal, CrystalClear, CrystalWare, DirectVPM, DIVA, FastEn, FastPath, FasText, FeatureChips, FilterJet, Get into it, Good Data, IntelliFilter, Laguna, Laguna3D, Matterhorn, MediaDAC, Mojave, MotionVideo, MVA, SimulSCAN, S/LA, SmartAnalog, SMASH, SofTarget, SoundFusion, Stargate, Systems in Silicon, TextureJet, True-D, TVTap, UXART, VisualMedia, VPM, V-Port, V-Port Manager, Voyager, WavePort, and WebSet are trademarks of Cirrus Logic, Inc ...