LQH4C100K04 MPS [Monolithic Power Systems], LQH4C100K04 Datasheet - Page 10

• Manufacturer Part Number: LQH4C100K04
• Description: 1.6MHz Synchronous Step-Down plus 200mA LDO
• Manufacturer: MPS [Monolithic Power Systems]

Switcher Input Capacitor Selection
The input capacitor (C
current drawn from the input and switching
noise from the device. The input capacitor
impedance at the switching frequency should
be less than the input source impedance to
prevent
passing to the input. Ceramic capacitors with
X5R
recommended because of their low ESR and
small
applications, a 4.7µF capacitor is sufficient.
Switcher Output Capacitor Selection
The output capacitor (C
voltage ripple small and ensures regulation loop
stability.
should be low at the switching frequency.
Ceramic capacitors with X5R or X7R dielectrics
are recommended. The output ripple ∆V
approximately:
Thermal Dissipation
Power dissipation should be considered when
both channels of the MP2101 provide maximum
output current at high ambient temperatures. If
the junction temperature rises above 150°C, the
two channels will shut down.
The junction-to-ambient thermal resistance of
the 10-pin QFN (3mm x 3mm) R
The maximum power dissipation is about 1.6W
when the MP2101 is operating in a 70°C
ambient temperature environment.
MP2101 Rev. 1.0
8/18/2006
∆
⎛
⎜
⎜
⎝
temperature
or
ESR
V
PD
high
OUT
The
MAX
TM
X7R
+
1
≤
8
=
frequency
output
×
V
150
f
OUT
OSC
50
V
o
dielectrics
1
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
1
coefficients.
IN
C
o
×
×
C
1
IN1
−
(
capacitor impedance
C
×
O1
/
V
70
) reduces the surge
W
f
O
IN
) keeps the output
OSC
1
o
1
switching
⎞
⎟
⎟
⎠
C
−
MP2101 – 1.6MHz SYNCHRONOUS STEP-DOWN PLUS 200mA LDO
×
=
V
ΘJA
L
OUT
1
6 .
are
W
1
is 50°C/W.
For
)
© 2006 MPS. All Rights Reserved.
×
current
www.MonolithicPower.com
highly
OUT
most
is
Start-Up Consideration
To ensure a smooth start-up of OUT1 and
OUT2, it is recommended that the enable
signals (EN1 and EN2) be asserted only after
the input power rails have been stabilized. If
EN1 and EN2 are tied to input rails directly, the
UVLO of the MP2101 will dictate when the part
starts switching. Since for certain systems, the
input
impedance
depending solely on UVLO to start the part may
cause input rail dip and output bounce. If the
system designer can not provide the enable
signal after input power rail is fully established,
it is recommended that EN1 and EN2 are
connected to the input power rail through a RC
delay network (as shown in Figure 2). The RC
time constant needs to be significantly large
compare to the ramp-up time of the input power
rail, which is usually of a few ms.
PC Board Layout
The high current paths (GND, IN1/IN2 and
SW1) should be placed very close to the device
with short, direct and wide traces. Input
capacitors should be placed as close as
possible to the respective IN and GND pins.
The external feedback resistors should be
placed next to the FB pins. Keep the switching
nodes SW1 short and away from the feedback
network.
supply
during
may
ramp
have
relatively
up,
therefore
high
10