IC61LV256-10JG ICSI [Integrated Circuit Solution Inc], IC61LV256-10JG Datasheet - Page 7

• Manufacturer Part Number: IC61LV256-10JG
• Description: 32K x 8 Hight Speed SRAM with 3.3V
• Manufacturer: ICSI [Integrated Circuit Solution Inc]

AC WAVEFORMS
WRITE CYCLE NO. 1
IC61LV256
Integrated Circuit Solution Inc.
AHSR027-0B
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%
4. Tested with OE HIGH.
Symbol
t
t
t
t
t
t
t
t
t
t
levels of 0 to 3.0V and output loading specified in Figure 1.
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold
timing are referenced to the rising or falling edge of the signal that terminates the Write.
tested.
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
(4)
(3)
(3)
ADDRESS
11/28/2003
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold
from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
D
OUT
WE
D
CE
IN
(CE Controlled, OE is HIGH or LOW)
DATA UNDEFINED
t
SA
Min. Max.
4.5
—
8
7
7
0
0
7
0
0
-8 ns
t
3.5
HZWE
—
—
—
—
—
—
—
—
—
t
VALID ADDRESS
AW
t
t
PWE1
PWE2
Min. Max.
t
t
10
10
—
8
8
0
0
5
0
0
SCE
-10 ns
WC
(1,2)
—
—
—
—
—
—
—
—
—
(1 )
4
HIGH-Z
(Over Operating Range)
t
Min. Max.
SD
12
12
—
8
8
0
0
6
0
0
DATA
-12 ns
—
—
—
—
—
—
—
—
—
6
IN
VALID
Min. Max.
15
10
10
15
—
0
0
7
0
0
-15 ns
t
HD
t
LZWE
—
—
—
—
—
—
—
—
—
7
t
HA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7