PE3282A PEREGRINE [Peregrine Semiconductor Corp.], PE3282A Datasheet - Page 6

• Manufacturer Part Number: PE3282A
• Description: 1.1 GHz/510 MHz Dual Fractional-N PLL IC for Frequency Synthesis
• Manufacturer: PEREGRINE [Peregrine Semiconductor Corp.]

PE3282A
Figure 3. PE3282A Functional Block Diagram
Functional Description
The Functional Block Diagram in Figure 2 shows a 21-
bit serial control register, a multiplexed output, and PLL
sections PLL1 and PLL2. Each PLL contains a fractional-N
main counter chain, a reference counter, a phase
detector, and an internal charge pump with on-chip
fractional spur compensation. Each fractional-N main
counter chain includes an internal dual modulus
prescaler, supporting counters and a fractional
accumulator.
Serial input data is clocked on the rising edge of Clock,
MSB first. The last two bits are the address bits that
determine the register address. Data is transferred into
the counters as shown in Table 7, PE3282A Register Set. If
the f
of shift register bit S
Clock onto the f
and compatible devices to be connected in a daisy-chain
configuration.
o
LD pin is configured as data out, then the contents
Clock
Data
o
LD pin. This feature allows the PE3282A
LE
f
f
in
in
f
f
f
in
r
in
1
1
2
2
20
are clocked on the falling edge of
Prescaler
Prescaler
32/33
16/17
Serial Control Interface
3 ð R
3 ð R
R
R
1
2
Counter
Counter
1
R
R
2
9
9
1
2
ð 511
ð 511
3 ð M
A
3 ð M
M
0 ð A
A
0 ð A
M
1
2
2
1
Counter
Counter
Counter
M
Counter
M
A
A
5
9
2
9
4
1
2
1
1
2
1
2
ð 511
ð 31
ð 15
ð 511
The PLL1 (RF) VCO frequency f
reference frequency f
(1) Note that A
greater than or equal to 1024 x (f
contiguous channels.
The PLL2 (IF) VCO frequency f
frequency f
(2) Note that A
greater than or equal to 256 x (f
contiguous channels.
F
PE3282A automatically reduces the fraction. For
example, if F
automatically reduced to 3/8. In this way, fractional
denominators of 2, 4, 8, 16 and 32 are available. F
the fractionality for PLL2 in the same manner.
1
sets PLL1 fractionality. If F
f
f
Detector
Detector
in
in
Control Logic
Control Logic
Phase
Phase
F
F
1 = [(32 x M
r
2 = [(16 x M
0 ð F
0 ð F
Prescaler
Prescaler
1
2
by the following equation:
1
Counter
Counter
= 12, then the fraction 12/32 is
F
C
F
C
5
1
2
5
1
2
1
2
11
21
ð 31
ð 31
must be less than M
must be less than M
r
by the following equation:
1
2
) + A1 + (F
) + A2 + (F
C
Compensation
C
Compensation
Multiplexer
1
12
22
in
Data Out
Fractional
Fractional
is an even number,
in
2 is related to the reference
f
o
1 is related to the
r
LD
Charge
Charge
/R
Pump
Pump
r
/R
1
2
2
/32)] x (f
/32)] x (f
) to obtain
1
1
2
) to obtain
. Also, f
. Also, f
Document 70/0002~07B
C
C
C
C
13
14
23
24
r
r
in
in
/R
/R
1 must be
2 must be
1
2
)
)
CP1
f
CP2
o
LD
2
sets