H6060 EMMICRO [EM Microelectronic - MARIN SA], H6060 Datasheet - Page 6

• Manufacturer Part Number: H6060
• Description: Self Recovering Watchdog
• Manufacturer: EMMICRO [EM Microelectronic - MARIN SA]

Typical Applications
Microprocessor Watchdog with Power-On Reset and Voltage Monitor
Timer Programming
With pin RC unconnected, the on-chip RC oscillator
together with its divider chain give a timeout T
typically 100
approximation for calculating component values is given
by the formula:
A resistor decreases and a capacitor increases the
interval to timeout. Excellent temperature stability of T
can be achieved by using external components. A precise
square wave of period 2 × T
The oscillator and watchdog timer start running when
both V
greater than V
They will remain running while both V
V
Copyright © 2004, EM Microelectronic-Marin SA
RES and RES when TCL is tied to either V
T
RL
TO
and V
R
If R
=
1 min.
⎡
⎢
⎢
⎢
⎢
⎣
IN
0.75
1
is in MΩ and C
is greater than V
DD
= 10 kΩ, C
+
is greater than V
5.5
R
ON
(32
ms.
(see Fig. 3).
+
+
V
C
DD
1 max.
1
R
To
)
1
⋅
1
−
2
in pF, T
1
= 1 µF
⎤
⎥
⎥
⎥
⎥
⎦
program
TO
SH
OFF
8.192
is generated at the outputs
(see Fig. 6) and V
(see Fig. 3).
TO
will be in ms.
different
IN
is greater than
DD
T
TO
or V
TO
,
DD
SS
an
TO
of
is
.
Timer Clearing and RES /RES Action
A negative edge or a negative pulse at the TCL input for
longer than 150 ns will reset the timer and set RES and
RES inactive. If a further TCL signal edge or pulse is
applied before T
inactive and the timer will again be reset to zero (see Fig.
5). If no TCL signal is applied before the T
period 2 × T
watchdog will remain in this state until the next TCL
signal appears, or until a fresh power-up sequence.
Combined Voltage and Timer Action
The combination of voltage and timer actions is illustrated
by the sequence of events shown in Fig. 6. One timeout
period after V
RES go inactive. A TCL pulse will have no effect until
this power-on reset delay is completed. After completing
the power-up sequence the watchdog timer starts acting.
If no TCL pulse occurs, RES and RES go active after
one timeout period T
period, without a timer clear pulse at TCL , RES and
RES change polarity providing square wave signals. A
and RES to go inactive. A voltage drop below the V
level overrides the timer and immediately forces RES ,
RES and SAVE active. Any further TCL pulse has no
effect until the next power-up sequence is completed.
RES and RES will start to generate square waves of
TCL pulse clears the watchdog timer and causes RES
6
IN
TO
reaches V
TO
starting with the inactive state. The
timeout, RES and RES will remain
TO
. After each subsequent timeout
SH
, during power-up, RES and
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H6060
TO
timeout,
RL