CH7005C-V ETC [List of Unclassifed Manufacturers], CH7005C-V Datasheet - Page 25

• Manufacturer Part Number: CH7005C-V
• Description: Digital PC to TV Encoder with Macrovision
• Manufacturer: ETC [List of Unclassifed Manufacturers]

CHRONTEL
Transfer Protocol
Both read and write cycles can be executed in “Alternating” and “Auto-increment” modes. Alternating mode
expects a register address prior to each read or write from that location (i.e., transfers alternate between address and
data). Auto-increment mode allows you to establish the initial register location, then automatically increments the
register address after each subsequent data access (i.e., transfers will be address, data data data...). A basic serial port
transfer protocol is shown in Figure 20 and described below.
1. The transfer sequence is initiated when a high-to-low transition of SD occurs while SC is high; this is the
2. The transfer sequence is terminated when a low-to-high transition of SD occurs while SC is high; this is the
3. Upon receiving the first START condition, the CH7005 expects a Device Address Byte (DAB) from the
4. After the DAB is received, the CH7005 expects a Register Address Byte (RAB) from the master. The
Device Address Byte (DAB)
R/W
Register Address Byte (RAB)
201-0000-025 Rev 2.1, 8/2/99
“START” condition. Transitions of address and data bits can only occur while SC is low.
“STOP” condition.
master device. The value of the device address is shown in the DAB data format below.
format of the RAB is shown in the RAB data format below (note that B7 is not used).
SD
SC
B7
B7
1
1
Condition
Start
AutoInc
B6
B6
1
Read/Write Indicator
“0”:
“1”:
Device ID
CH7
master device will write to the CH7005 at the register location specified by the address
AR[5:0]
master device will read from the CH7005 at the register location specified by the
address AR[5:0].
R/W*
Figure 20: Serial Port Transfer Protocol
AR[5]
B5
B5
8
I
1
2
C
acknowledge
CH7005
ACK
9
AR[4]
B4
B4
0
Data
1 - 8
1
acknowledge
ACK
AR[3]
CH7005
B3
B3
9
1
AR[2]
Data n
B2
B2
1 - 8
0
acknowledge
CH7005
ACK
9
AR[1]
B1
B1
1
CH7005C
Condition
AR[0]
R/W
B0
B0
Stop
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