EM65100AGH EMC [ELAN Microelectronics Corp], EM65100AGH Datasheet - Page 50

• Manufacturer Part Number: EM65100AGH
• Description: 69 COM/ 101 SEG 4 Gray Level STN LCD Driver
• Manufacturer: EMC [ELAN Microelectronics Corp]

In each operation mode, the following increment operation is performed:
(i)
(ii)
8.2.11 Power Control Register
(At the tine of reset: {AMPON, HALT, DCON, ACL}=0H, read address: BH)
ACL
The internal circuit can be initialized.
ACL = “0”: Normal operation
ACL = “1”: Initialization ON
When the reset operation begins internally after ACL register sets to “1”, the ACL register is automatically cleared to “0”.
The internal reset signal has been generated with a clock (built-in oscillation circuit or CK input) for the display. Therefore,
install the WAIT period for the display clock two cycles at least. After WAIT period, next operation can handle. Since
built-in oscillation circuit ,the setting of the ACL register becomes the invalidity.
DCON
The internal booster circuit is set ON/OFF
DCON = “0”: Booster circuit OFF
DCON=”1”: Booster circuit ON
HALT
The conditions of power saving are set ON/OFF by this command.
HALT = “0”: Normal operation
HALT=”1”: Power-saving operation
When setting in the power-saving state, the consumed current can be reduced to a value near to the standby current.
* This specification is subject to be changed without notice.
D7
1
In the monochrome display mode, 0H to 19H are available for X-addresses in the access area.
When gradation display mode and 8-bit access are selected: Address are incremented as described above.
When monochrome display mode and 8-bit access are selected:
D6
0
D5
1
D4
1
AMP
ON
D3
HAL
D2
T
DCO
D1
N
ACL
D0
69 COM/ 101 SEG 4 Gray Level STN LCD Driver
CSB
0
RS
1
RDB WRB RE2
1
0
0
RE1
2005/3/8 (V0.6)
0
RE0
0
EM65100
50