DTR-1250-SM-GB-H8-HS-C490 OPLINK [OPLINK Communications Inc.], DTR-1250-SM-GB-H8-HS-C490 Datasheet - Page 4

• Manufacturer Part Number: DTR-1250-SM-GB-H8-HS-C490
• Description: Multi-rate 5V Very Long Haul CWDM GBIC Transceivers
• Manufacturer: OPLINK [OPLINK Communications Inc.]

Application Notes
Connection of the GBIC transceiver to the host system: The
GBIC’s 20-pad connector and two guide tabs connected to the
transceiver’s circuit ground connect the GBIC to the host
system. The two ground tabs make contact to the host circuit
ground before the connector pad and discharge any possible
component-damaging static electricity. Additionally, surge
currents are eliminated by using a special slow start circuit
and two-stage contact sequence where operational signals
and grounds make contact prior to the power supply (as
specified in the GBIC specification, Rev. 5.5).
Electrical interface: All signal interfaces are compliant with
the GBIC specification, Rev. 5.5. The high speed DATA
interface is differential AC-coupled and can be directly
connected to either a 5V or 3.3V SERDES IC. All low speed
control and sense input/output signals are open collector TTL
compatible and should be pulled up with a 4.7 - 10kΩ resistor
on the host board.
RX_LOS: The RX LOSS OF SIGNAL circuit monitors the level
of the incoming optical signal and generates a logic HIGH
when an insufficient photocurrent is produced.
TX_FAULT: The output indicates LOW when the transmitter
is operating normally, and HIGH when the transmitter or laser
current is excessive. TX_FAULT is an open collector/drain
output and should be pulled up with a 4.7 - 10kΩ resistor on
the host board.
Example of host board schematic
VDD
(5V)
(internally connected to GND)
+TX_DAT
-TX_DAT
TX_DISABLE
TTL LOW
(<0.2
1 H coil or ferrite bead
DTR-1250-SM-GB-H8-HS-CWDM-MR
µ
+
0.1
Ω
10
series resistance)
+
+
75
75
10
10
Ω
Ω
line
line
0.1
0.1
15
16
18
19
7
2,3,8,9,11,14,17,20
4
4
GBIC
TX_DISABLE: When the TX_DISABLE pin is at logic HIGH,
the transmitter optical output is disabled (less than -35dBm).
Serial Identification: The DTR-1250-SM-GB-H8-HS-CWDM-
MR transceivers are compliant with Annex D (Module
Definition 4) of the GBIC specification, Rev. 5.5, which defines
the Serial Identification Protocol.
The module definition of GBIC is indicated by the three
module definition pins, MOD_DEF(0), MOD_DEF(1) and
MOD_DEF(2). Module Definition 4 specifies a serial definition
protocol with a two-wire I
MOD_DEF(1:2) appear as NC (no connection), and
MOD_DEF(0) is TTL LOW. When the host system detects
this condition, it activates the serial protocol and generates
the serial clock signal (SCL). The negative edge clocks data
from the GBIC EEPROM.
The serial data signal (SDA) is for serial data transfer. The host
uses SDA in conjunction with SCL to mark the start and end of
serial protocol activation.
The data transfer protocol and the details of the mandatory
and vendor specific data structures are defined in Annex D of
the GBIC specification, Rev. 5.5.
Power supply and grounding: The power supply line should
be well-filtered. All 0.1µF power supply bypass capacitors
should be as close to the GBIC transceiver module as possible.
5
6
10
13
12
1
TX_FAULT
SDA
4.7 - 10kΩ
SCL
75
75
Ω
Ω
line
line
VCC (HOST)
2
C serial interface; upon power up,
to 75
to 75
+RX_DAT
-RX_DAT
4.7 - 10kΩ
RX_LOS
Ω
Ω
load
load
21737-0609, Rev. C
04/05/2006