UT54LVDS032LV AEROFLEX [Aeroflex Circuit Technology], UT54LVDS032LV Datasheet
UT54LVDS032LV
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UT54LVDS032LV Summary of contents
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... EN EN Figure 1. UT54LVDS032LV Quad Receiver Block Diagram INTRODUCTION The UT54LVDS032LV Quad Receiver is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400.0 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology ...
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... OUT The UT54LVDS032LV differential line receiver is capable of detecting signals as low as 100mV, over common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift +1V around this center point. ...
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... HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The UT54LVDS032LV is a quad receiver device, and if an application requires only receivers, the unused channel(s) inputs should be left OPEN ...
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ABSOLUTE MAXIMUM RATINGS (Referenced SYMBOL I/O T STG Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is ...
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DC ELECTRICAL CHARACTERISTICS (V = 3.3V + 0.3V; -55 C < T < +125 SYMBOL PARAMETER V High-level input voltage IH V Low-level input voltage IL V Low-level output voltage OL V High-level output voltage OH I ...
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AC SWITCHING CHARACTERISTICS (V = +3.3V + 0.3V - +125 SYMBOL 6 Differential Propagation Delay High to Low t PHLD CL = 10pf (figures 4 and 5) 6 Differential Propagation Delay Low to ...
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Generator 5 0 Figure 4. Receiver Propagation Delay and Transition Time Test Circuit or Equivalent Circuit R IN- 0V Differential R IN+ t PLHD 50% R OUT 20% t TLH Figure 5. Receiver Propagation Delay and Transition Time Waveforms R ...
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EN R IN+ R IN- Figure 6. Receiver Three-State Delay Test Circuit or Equivalent Circuit EN when when Output when V = -100mV ID Output when V = +100mV ID Figure ...
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Notes: 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance to MIL-PRF-38535. 4. Package dimensions and symbols are similar to MIL-STD-1835 variation ...
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... ORDERING INFORMATION UT54LVDS032LV QUAD RECEIVER: UT 54LVDS032LV Notes Lead finish (A, must be specified “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold Prototype flow per UTMC Manufacturing Flows Document. Tested only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed ...
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... UT54LVDS032LV QUAD RECEIVER: SMD 98652 ** * * * 5962 - Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: ( lead Flatpack (dual-in-line) Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 02 = LVDS Receiver, 300k, 500k and 1M Rad(Si LVDS Receiver, 100k Rad(Si) ...