UT54LVDS217 AEROFLEX [Aeroflex Circuit Technology], UT54LVDS217 Datasheet
UT54LVDS217
Related parts for UT54LVDS217
UT54LVDS217 Summary of contents
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... Mbps per LVDS data channel. Using a 75MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/sec). The UT54LVDS217 Serializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size. All pins have Cold Spare buffers. These buffers will be high ...
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... LVDS V 28 PLL GND 27 PWR DWN LVDS GND 26 TxCLK IN 25 TxIN20 LVDS CABLE MEDIA DEPENDENT SHIELD Figure 3. UT54LVDS217 Typical Application Description I/O No. TTL level input I 21 Positive LVDS differential data output O 3 Negative LVDS differential data output O 3 TTL level clock input. The rising edge acts ...
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ABSOLUTE MAXIMUM RATINGS (Referenced SYMBOL I/O T STG Θ Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This ...
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DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CMOS/TTL DC SPECIFICATIONS V High-level input voltage IH V Low-level input voltage IL High-level input current Low-level input current IL Input clamp voltage Cold Spare Leakage current CS LVDS ...
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AC SWITCHING CHARACTERISTICS (V = 3.0V to 3.6V -55°C to +125°C) DD SYMBOL 2 LVDS Low-to-High Transition Time (Figure 5) LLHT 2 LVDS High-to-Low Transition Time (Figure 5) LHLT 2 Transmitter Output Pulse Position for Bit 0 (Figure ...
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... TxCLK IN TxIN AC TIMING DIAGRAMS TxOUT+ 5pF 100Ω TxOUT- T Figure 4. Test Pattern Vdiff=(TxOUT+) - (TxOUT-) 20% Vdiff Figure 5. UT54LVDS217 Output Load and Transition Times 90% 10% TXCLK IN TCIT Figure 6. UT54LVDS217 Input Clock Transition Time 80% LLHT 90% 10% TCIT 80% 20% LHLT ...
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... TxOUT1 TxOUT2 TxCLK OUT TIME Figure 7. UT54LVDS217 Channel-to-Channel Skew TCIP TCIH TCIL TSTC SETUP Figure 8. UT54LVDS217 Setup/Hold and High/Low Times TxCLK IN V TCCD TxCLK OUT Figure 9. UT54LVDS217 Clock-to-Clock Out Delay Vdiff= 0V Sample on L-H Edge THTC HOLD ...
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... Previous Cycle TxOUT2 / TxIN15-1 TxIN14-1 RxIN2 TxOUT1 / TxIN8-1 TxIN7-1 RxIN1 TxOUT0 / TxIN1-1 TxIN0-1 RxIN0 Figure 11. UT54LVDS217 Parallel TTL Data Inputs Mapped to LVDS Outputs TPLLS Figure 10. UT54LVDS217 Phase Lock Loop Set Time Next Cycle TxIN20 TxIN19 TxIN18 TxIN17 TxIN13 TxIN12 TxIN11 TxIN10 TxIN6 ...
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POWER DOWN TxCLK IN TxOUT Figure 12. Transmitter Powerdown Delay TxCLK OUT / Differential Previous Cycle TxOUT2 / TxIN15-1 TxIN14-1 (Single ended) TxOUT1 / TxIN8-1 TxIN7-1 Single ended TxOUT0 / TxIN1-1 TxIN0-1 Single ended TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 ...
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Generator 50Ω Driver Enabled Figure 14. Driver V and V Test Circuit or Equivalent Circuit OUT+ 20pF 100Ω 20pF D OUT- ...
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PACKAGING All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Lead position and colanarity are not measured. ...
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... Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow Package Type: (U) = 48-lead Flatpack (dual-in-line) Access Time: Not applicable Device Type: UT54LVDS217 Serializer ° C only. Lead finish is GOLD ONLY. Radiation neither 12 ° C, room temp, and ...
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... UT54LVDS217 Serializer: SMD 5962 - 01534 * * * ** Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: ( lead Flatpack (dual-in-line) Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 01 = 50MHz LVDS Serializer (contacat factory 75MHz LVDS Serializer Drawing Number: 01534 ...
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