16F84 MICROCHIP [Microchip Technology], 16F84 Datasheet - Page 43

• Manufacturer Part Number: 16F84
• Description: 18-pin Flash/EEPROM 8-Bit Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

8.4
A Power-on Reset pulse is generated on-chip when
V
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to V
external RC components usually needed to create
Power-on Reset. A minimum rise time for V
met for this to operate properly. See Electrical Specifi-
cations for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be meet to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions
are met.
For additional information, refer to Application Note
AN607, " Power-up Trouble Shooting ."
The POR circuit does not produce an internal reset
when V
8.5
The Power-up Timer (PWRT) provides a fixed 72 ms
nominal time-out (T
Figure 8-11,
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT delay allows the V
able level (Possible exception shown in Figure 8-13).
A configuration bit, PWRTE, can enable/disable the
PWRT. See either Figure 8-1 or Figure 8-2 for the oper-
ation of the PWRTE bit for a particular device.
The power-up time delay T
chip due to V
See DC parameters for details.
8.6
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT
Figure 8-12 and Figure 8-13). This ensures the crystal
oscillator or resonator has started and stabilized.
The OST time-out (T
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When V
T
V
(Figure 8-13), an external power-on reset circuit may
be necessary (Figure 8-9).
PWRT
DD
DD
1998 Microchip Technology Inc.
rise is detected (in the range of 1.2V - 1.7V). To
has reached its final value. In this case
DD
time-out and T
DD
Power-on Reset (POR)
delay
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
declines.
rises very slowly, it is possible that the
DD
Figure 8-12
, temperature, and process variation.
ends
OST
PWRT
OST
) is invoked only for XT, LP and
(Figure 8-10,
) from POR (Figure 8-10,
PWRT
time-out will expire before
and
DD
will vary from chip to
DD
to rise to an accept-
Figure 8-13). The
. This will eliminate
Figure 8-11,
DD
must be
FIGURE 8-9:
Note 1: External Power-on Reset circuit is required
2: R < 40 k is recommended to make sure
3: R1 = 100 to 1 k will limit any current
V
DD
only if V
diode D helps discharge the capacitor
quickly when V
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5 A). A larger voltage drop will
degrade V
flowing into MCLR from external
capacitor C in the event of an MCLR pin
breakdown due to ESD or EOS.
D
V
DD
EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
V
R
DD
DD
C
IH
power-up rate is too slow. The
POWER-UP)
level on the MCLR pin.
DD
R1
PIC16F8X
powers down.
MCLR
PIC16FXX
DS30430C-page 43