HEF4002BTD Philips, HEF4002BTD Datasheet - Page 10
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HEF4002BTD
Manufacturer Part Number
HEF4002BTD
Description
Logic, Standard, soic, NOR Gates, Logic Gates, Single, dual, Semiconductors and Actives, gate, ic
Manufacturer
Philips
Datasheet
1.HEF4002BTD.pdf
(13 pages)
Philips Semiconductors
January 1995
handbook, full pagewidth
In the waveforms above the active transition of the clock input is going from LOW to HIGH and
the active level of the forcing signals (SET, CLEAR and PRESET) is HIGH.
The actual direction of the active transition of the clock input and the actual active levels of the
forcing signals are specified in the individual device data sheet.
Fig.7 Set-up times, hold times, recovery times and propagation delays for sequential logic circuits.
OUTPUT
PRESET
CLOCK
RESET,
INPUT
INPUT
INPUT
DATA
SET,
10%
50%
t su
50%
t R
t r
10%
50%
t PLH
90%
t WCPH
t hold
50%
90%
t TLH
t f
10
t WCPL
t su
t PHL
t hold
t THL
Family Specifications
MGK561
V DD
V SS
V DD
V SS
V OH
V OL
V DD